From patchwork Sat Jan 26 04:10:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 156666 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1120834jaa; Fri, 25 Jan 2019 20:11:21 -0800 (PST) X-Google-Smtp-Source: ALg8bN6+RY4jlkLprfJS+IUHuvroE1+ol9IP5P7+HVLARdetUmO6EOFUYTLezVBXCIOWKGu2tgU0 X-Received: by 2002:a17:902:3143:: with SMTP id w61mr14021768plb.253.1548475881208; Fri, 25 Jan 2019 20:11:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548475881; cv=none; d=google.com; s=arc-20160816; b=F4ULFbehStfdNr+IVm8BNkVrlAdQS37x3F21VZfb+qEZ2CEU9LgjdnNz/ucjuRWWBK BHJG6drsigOOU0xLEK/P7v/cr3TzAMQdGENtdyuOj+YeGJwwwzgSbxYXxP5DPZxV9GUL ujnxvnLWTBiFGLCuCsHXvSeRumr7UYEJ6+I3JnGbEaNh82Qxjl7WsU7HpwOUaY7gK4/J 8TZsXS8/kvu9J6Dmcc+Hf556BHFB+RF/R+QTdXCBudB0yjePQpN4xTSilLIatu117XaT /SqbxrlyhtEjWNMmu7s22TNxa+SDBda055pnvM5Hak13qp3jQPMGAEYm3KC5O8fp5SBj NK9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=6n/1pZVNoLogyX+K/gR163sI6cwrL7Mu1c32gRBtLNk=; b=TLEZJYcgBSVM7glaUMLb10klkMxYqSn7fz0ZxLWuHLdAebfRBdzTmHWj/VOvOL+Sju KdWWYN5k6MrtmfMcu8SlKivjdCn1ECpmgRna06R1Czj9CEmZfLtiXgoFcgdFBF6Yxfwt QUNKH8pZlOnZjOoqdLUjMJ5WRXCPjSYBVSMav2wEG1QLx5gPa7zLchyDgeSNmI+XWx+0 MYuKrU8Cq+M4FITFhQGvkvuCdItaPRbS71I6q5PS2RJzuT68Eg5T4lIQPY8WuNzAlNX/ W9TIV3J2a22ZxIfjdatXVAGcTdOhq9sLGOsHwoNvXWuY660K7cbUhqa6O6AU8sUEU46p MVAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lraksk99; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 41si22526838plf.347.2019.01.25.20.11.20; Fri, 25 Jan 2019 20:11:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lraksk99; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729680AbfAZELU (ORCPT + 7 others); Fri, 25 Jan 2019 23:11:20 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:39815 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729676AbfAZELU (ORCPT ); Fri, 25 Jan 2019 23:11:20 -0500 Received: by mail-pg1-f195.google.com with SMTP id w6so5009302pgl.6 for ; Fri, 25 Jan 2019 20:11:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6n/1pZVNoLogyX+K/gR163sI6cwrL7Mu1c32gRBtLNk=; b=Lraksk99Qc/bC8ojQxeOsDr8dDsOFF+pmDXRQUpvi12Kr9E6bWep1TFsPLaWPqhx9s ivZL7SjJWV5VdhtUO7vMvFO9Vi29dYJD6pe3xG32YMUrVAYt8NQ/jzmTqezEdRc5dJtP puGEn7GNNh45dQMYt1hk71cj1+VGU0Ky+tbBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6n/1pZVNoLogyX+K/gR163sI6cwrL7Mu1c32gRBtLNk=; b=JRfRCsbzTYOyGxbmyUfqXk6CpnS9oUz6yYajwACR32QZlYilFrABTQr8X9ZHNo98bO r3mXOLZhA/CanGV4Z+CA9Y5Id4zLkEyYsDqHZelgjGcHnKv42hb9kVBGxPVDUA+N6qu7 hLrPtOh4HXverbwwssD1F/Xs4HnpMVUeI+fMHivUol7T0s87vzZSaXIzFnwZxsle3Yv7 diJtRIKDXcuM9//EvO4v+DN1Kja1Cbn+4IoLqwUqBkhbsO7uSb0WrU4lxsjNLXkHHG7/ IY5N/iXZmz8tKK1kETPxhmHOIUD4CVrMe9IuJDV7+gZth5A7xVklL0B/EEwI6ARM37pD WGdw== X-Gm-Message-State: AJcUukeHZlBhKI0Oxw9q2Hy8sYQxbi7Br98Ic+oplCWLIqd/wfhcSKli AOtjWvDfWda/GFi/Zum3XaFr X-Received: by 2002:a63:f615:: with SMTP id m21mr12605200pgh.428.1548475879189; Fri, 25 Jan 2019 20:11:19 -0800 (PST) Received: from localhost.localdomain ([2409:4072:905:e69d:b1bd:9891:c622:302d]) by smtp.gmail.com with ESMTPSA id h129sm75099676pfb.110.2019.01.25.20.11.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Jan 2019 20:11:18 -0800 (PST) From: Manivannan Sadhasivam To: robh+dt@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, amit.kucheria@linaro.org, Manivannan Sadhasivam Subject: [PATCH 3/5] arm64: dts: bitmain: Add BM1880 SoC support Date: Sat, 26 Jan 2019 09:40:39 +0530 Message-Id: <20190126041041.13173-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190126041041.13173-1-manivannan.sadhasivam@linaro.org> References: <20190126041041.13173-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor Processor subsystem. Only ARM Cortex A53 Application processor subsystem support is enabled for now. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bitmain/bm1880.dtsi | 119 ++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 arch/arm64/boot/dts/bitmain/bm1880.dtsi -- 2.17.1 diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 4690364d584b..5bc7533a12c7 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -7,6 +7,7 @@ subdir-y += amd subdir-y += amlogic subdir-y += apm subdir-y += arm +subdir-y += bitmain subdir-y += broadcom subdir-y += cavium subdir-y += exynos diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi new file mode 100644 index 000000000000..55a4769e0de2 --- /dev/null +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include + +/ { + compatible = "bitmain,bm1880"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secmon@100000000 { + reg = <0x1 0x00000000 0x0 0x20000>; + no-map; + }; + + jpu@130000000 { + reg = <0x1 0x30000000 0x0 0x08000000>; // 128M + no-map; + }; + + vpu@138000000 { + reg = <0x1 0x38000000 0x0 0x08000000>; // 128M + no-map; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@50001000 { + compatible = "arm,gic-400"; + reg = <0x0 0x50001000 0x0 0x1000>, + <0x0 0x50002000 0x0 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + uart0: serial@58018000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x58018000 0x0 0x2000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@5801A000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x5801a000 0x0 0x2000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@5801C000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x5801c000 0x0 0x2000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@5801E000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x5801e000 0x0 0x2000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +};