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[209.132.180.67]) by mx.google.com with ESMTP id e125si2097963pfe.14.2019.01.14.19.34.16; Mon, 14 Jan 2019 19:34:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HHUtGV6B; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728044AbfAODeP (ORCPT + 7 others); Mon, 14 Jan 2019 22:34:15 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:36937 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728040AbfAODeP (ORCPT ); Mon, 14 Jan 2019 22:34:15 -0500 Received: by mail-pl1-f195.google.com with SMTP id b5so619618plr.4 for ; Mon, 14 Jan 2019 19:34:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QzEw+0c7YCMrIJx0PSwB5TjdR5ksSYaunb0Z3JfV66A=; b=HHUtGV6Bj0Zj+6v3TzOmsCTcz3nUIF8RYPXUoENgTw83quUwGId8YxiD/vXr4KDxru 7cwVtubU9A24OMrCre37l5/BsWqQt/E+iOga54NjfzCK957vp8nDoTOdF3fck1pSqqu8 tUrzUrT+5yNofk77YiSO/OFIh/QyUHAbQJeP0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QzEw+0c7YCMrIJx0PSwB5TjdR5ksSYaunb0Z3JfV66A=; b=FOD8BYIsX5J31w9zpjciZk9dWBT5wYm2khcPTGYMztMG2aqsuO6h2oKNI059ovt6Q4 EWl+xCkvqU+A9FXc8cRG+QtN6E2OHnePSjJKe+3gUYUEAQ01qoxHNk0EdX/8iUVZWmA8 80427FdL5/quFXsjEEz2WQLPYQKJqa94n78Za/hEWs50VV1CwSnT3shtjL/5wZFwqGCd 76QXGozsAcWRA+QsKbBLjY5smG1rufmXOYGB81YUL5HE0CjZ3R6ac6HY0daQERaQpWXU abEOd/4KOZNIke8CPPbZyn+zO4y4fof/Yo57cVgCYeGioHa9MugFo8yd517ZLAuTBp2r 9gCQ== X-Gm-Message-State: AJcUukdxhvOFStFP8FL8ojOPIA9P9UuuZZqJgsfXvbIhzTD6JvDZFxQ3 uygnIA8WLKkNtaFQ4fCCK0Fe X-Received: by 2002:a17:902:2868:: with SMTP id e95mr1891450plb.317.1547523254819; Mon, 14 Jan 2019 19:34:14 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6084:4813:7cd6:42d1:f14c:3e90]) by smtp.gmail.com with ESMTPSA id s9sm2137023pgl.88.2019.01.14.19.34.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jan 2019 19:34:14 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, afaerber@suse.de, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Manivannan Sadhasivam , Edgar Bernardi Righi Subject: [PATCH v2 3/6] ARM: dts: Add CMU support for Actions Semi Owl S500 SoC Date: Tue, 15 Jan 2019 09:03:37 +0530 Message-Id: <20190115033340.25016-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190115033340.25016-1-manivannan.sadhasivam@linaro.org> References: <20190115033340.25016-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Clock Management Unit (CMU) support for Actions Semi Owl family S500 SoC. Signed-off-by: Edgar Bernardi Righi [Mani: Fixed commit message and DTS] Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5ceb6cc4451d..aa758538de8c 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -3,8 +3,10 @@ * Actions Semi S500 SoC * * Copyright (c) 2016-2017 Andreas Färber + * Copyright (c) 2018 Edgar Bernardi Righi */ +#include #include #include @@ -70,6 +72,12 @@ #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -124,6 +132,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0120000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART0>; status = "disabled"; }; @@ -131,6 +140,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0122000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART1>; status = "disabled"; }; @@ -138,6 +148,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0124000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART2>; status = "disabled"; }; @@ -145,6 +156,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0126000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART3>; status = "disabled"; }; @@ -152,6 +164,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0128000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART4>; status = "disabled"; }; @@ -159,6 +172,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012a000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART5>; status = "disabled"; }; @@ -166,9 +180,17 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012c000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART6>; status = "disabled"; }; + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>;