From patchwork Mon Jan 14 13:24:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155484 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657835jaa; Mon, 14 Jan 2019 05:27:49 -0800 (PST) X-Google-Smtp-Source: ALg8bN70AUe8P69zn+RCcsp1K4W7MOJAz761OjwxYde9+SFap0EQXNbBGMb2wiCfiaGyYZcrhkEn X-Received: by 2002:a63:6103:: with SMTP id v3mr12066959pgb.75.1547472469539; Mon, 14 Jan 2019 05:27:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472469; cv=none; d=google.com; s=arc-20160816; b=vn1ff6A1EtGpoqgszzoPK/pWEUpSJ7QmtGIWHdYHqACItkp7eykL7+7ovLhmpWkZpQ 5n/9wsf5gxpmsbUhUja7H8BV4Sj46yMxYh7O1NYDLSLfEdrkO2MacPowWZyBsokOwJtm jrO42kb3ZCU8mW1Lu2v+RF61aqn6JsJII3zTBaj+Lv6umvWCr31DsW/4WmO46IM9V1La XhuAeoKNgGRjgoMPH6ZZP0bsfvvGB86cbLydEWLfAq9H4fvFBa2tU8Ul5IFV1DQel2I7 /fvUzXEQj8+LkMUMlvUyB+p2bUdrgbYhDnv7Og7YBA1GhjAVSA4WJHlqYcPMl5hFiMji ViJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=CF5ivThAeVhsXGcV5WpV6w68ilrQQqK8YE1SR4Z9I10=; b=LMvq/CAubMW5BOe3GbT7h5k//vET2ZwbCIAZ5Iht0MIvzEbctz234yD0VfOMd4ZHdF bvdteM5gQcczjBAby3n0GkRTDLaMbg8Mk0xE9cZ8zNgYT1akRgcvHGdFSGyQntnY+onk uCz+T8YLLMlimvKI6wYl8f4lTLbiX9PIJAxIXGVd6iJXDXzQwCfxxXTTpPhGN2jAYaNk Ak00Iu0wvIAAsAFDMF2L75ihoHD2apZPzFi1zMjhVKzHObS5DAfLNUZBNtlKeLPVOu5y HIRuDnOGpw20g6/w8pEN5Cb22zPGS432qYQvqrcA/GlRa44x5/p54K0r727gsG/pwA2t hHTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tk77drck; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t20si331011pgl.211.2019.01.14.05.27.49; Mon, 14 Jan 2019 05:27:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tk77drck; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726826AbfANN1s (ORCPT + 7 others); Mon, 14 Jan 2019 08:27:48 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41154 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726717AbfANN1r (ORCPT ); Mon, 14 Jan 2019 08:27:47 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQh1v041581; Mon, 14 Jan 2019 07:26:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472403; bh=CF5ivThAeVhsXGcV5WpV6w68ilrQQqK8YE1SR4Z9I10=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tk77drck6OKnLY9dkDBCKf0sySURytF9x0xxMOPFRCwcQZacNAStG107CmJDsQSmR r9+a5K2+EQ8KCsvpdbW4C/MY0hSXsdSyzqEbAPOAFj0g958OSBIGxdAPUCIUsSc3kt WtPG9Dy6s5YO1Q06AsX4zxT97WE4I625be1FHFCQ= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQhtG089758 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:43 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:42 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:42 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWi028516; Mon, 14 Jan 2019 07:26:38 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Date: Mon, 14 Jan 2019 18:54:22 +0530 Message-ID: <20190114132424.6445-23-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configre a aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 47cc06bac91f..f557e83bc34c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; + unsigned int aligned_offset; u16 msg_ctrl, msg_data; u32 msg_addr_lower, msg_addr_upper, reg; u64 msg_addr; @@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_readw_dbi(pci, reg); } - msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; + aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); + msg_addr = ((u64)msg_addr_upper) << 32 | + (msg_addr_lower & ~aligned_offset); ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, epc->mem->page_size); if (ret) return ret; - writel(msg_data | (interrupt_num - 1), ep->msi_mem); + writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);