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[209.132.180.67]) by mx.google.com with ESMTP id z6si42577982pgl.109.2018.12.31.10.56.00; Mon, 31 Dec 2018 10:56:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="drYNuZs/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727808AbeLaSz6 (ORCPT + 7 others); Mon, 31 Dec 2018 13:55:58 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:40094 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727807AbeLaSz6 (ORCPT ); Mon, 31 Dec 2018 13:55:58 -0500 Received: by mail-pg1-f194.google.com with SMTP id z10so12944158pgp.7 for ; Mon, 31 Dec 2018 10:55:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QzEw+0c7YCMrIJx0PSwB5TjdR5ksSYaunb0Z3JfV66A=; b=drYNuZs/jBj1/vLtblqax09zFggcbQ8stoB/0bqktqAbJghWOyVWDjfuk6tmVg1J2s X+Q7MfHl/fcPYdKUIpFFLoKrvYDrFbt2gNFfphH1op8jnamf/0s/e0gTPomNVNeegLz8 KRmQy+IdMAPJ2LgDEdt5zhl71aALwwOXHnzZs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QzEw+0c7YCMrIJx0PSwB5TjdR5ksSYaunb0Z3JfV66A=; b=gZ/JlmuaDmTmU+YHXhnc+9mFI4bhhcCQFQOD9yXoAVl4pymoXSiDHnG4pw+Q/Y5J7Z A18EWvd984eA0eUjJYfgsQBI17019rr7PJSYOLo+amAB6LLfEFAdIxo/D8pPyfYC0qsC Rcvbnerjagef5y9t/8hi3eC7ttBc2PsCzEyt81McmOhIw1xb3A9DVwih57gqdyEpTYGC v4+0nnD456KQAUI8c76kjHbJKN/X2ybwX7/RnItiHcuY3go9JBUO789khdi/U0PetazJ YaFwu0tRfLXmw9AeGzLg7c9HvpX9Wx0Fyd+fRRvHwY4kw2RS4iCnhRt7B39vDuuiUrqm Iriw== X-Gm-Message-State: AJcUukexMc0mKYLpgqJULsGrHNt11XqSENIr04eJ9uWb5hwbmtBBCR7I MalZYbXU5J7iI6B6Sn0ckPFW X-Received: by 2002:a63:9749:: with SMTP id d9mr8237520pgo.415.1546282557427; Mon, 31 Dec 2018 10:55:57 -0800 (PST) Received: from localhost.localdomain ([2405:204:7440:b882:8d58:e15f:9ff4:efc2]) by smtp.gmail.com with ESMTPSA id s9sm66146224pgl.88.2018.12.31.10.55.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Dec 2018 10:55:56 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, afaerber@suse.de, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Edgar Bernardi Righi Subject: [PATCH 3/6] ARM: dts: Add CMU support for Actions Semi Owl S500 SoC Date: Tue, 1 Jan 2019 00:25:14 +0530 Message-Id: <20181231185517.18517-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> References: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Clock Management Unit (CMU) support for Actions Semi Owl family S500 SoC. Signed-off-by: Edgar Bernardi Righi [Mani: Fixed commit message and DTS] Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5ceb6cc4451d..aa758538de8c 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -3,8 +3,10 @@ * Actions Semi S500 SoC * * Copyright (c) 2016-2017 Andreas Färber + * Copyright (c) 2018 Edgar Bernardi Righi */ +#include #include #include @@ -70,6 +72,12 @@ #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -124,6 +132,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0120000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART0>; status = "disabled"; }; @@ -131,6 +140,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0122000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART1>; status = "disabled"; }; @@ -138,6 +148,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0124000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART2>; status = "disabled"; }; @@ -145,6 +156,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0126000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART3>; status = "disabled"; }; @@ -152,6 +164,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0128000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART4>; status = "disabled"; }; @@ -159,6 +172,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012a000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART5>; status = "disabled"; }; @@ -166,9 +180,17 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012c000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART6>; status = "disabled"; }; + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>;