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[209.132.180.67]) by mx.google.com with ESMTP id v32-v6si22622254pgk.16.2018.11.14.01.00.47; Wed, 14 Nov 2018 01:00:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TgYxxRQA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732198AbeKNTDF (ORCPT + 6 others); Wed, 14 Nov 2018 14:03:05 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:54146 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732220AbeKNTDE (ORCPT ); Wed, 14 Nov 2018 14:03:04 -0500 Received: by mail-wm1-f68.google.com with SMTP id f10-v6so14557660wme.3 for ; Wed, 14 Nov 2018 01:00:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cw/K1SBDEn5L1Ca0s15yo5xPQT5iLoDouJnTbDSOJFo=; b=TgYxxRQAF9MJBhn0TF7EBA5swl+SSQHJjoGjtfkZH+0fSgAvqGZBpUskK8iYSIih5o iBtXQibZW0avDxAYG43cscoiCOKRVkT6ptpjXGRjvXTw8ETovZ3trmgK9qes6v7/lYv4 nhB97RFeTxyxv7DmGkiA+uhmMXeGzo6GoCh7g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cw/K1SBDEn5L1Ca0s15yo5xPQT5iLoDouJnTbDSOJFo=; b=O4zjiCLqCK9/RForrozR0KRrnrBZDrIJWERD8jntYCoRjAR7kA4vQTgbVGPbMhr1/W rrWpI4XR0+A/FThPec/ZVyME8t/GIFBxssOWARZ43MDq8fmjcJucpEo9esrBRHXzEyzU hIErgrVemOvXh8vJYMwpdkBFydYAA9QtMZY65q9EcfCemi8qi/Mwoj3Fz51lKr9aXIGu S7sPGfgGrjGbtaNWQQIhMKlyVAE46BfBe9DJBBvBaqRsF8y/U22ZN0lXZQEvQ0DBeJs/ h+wTRTEkedW9S1Lv/mXtouuncsyZqST1hQakj1IC2+ff55rGI5YVijaJOLpduYSssd6m ON4g== X-Gm-Message-State: AGRZ1gIvX3lBSFNBBIK6VW+QuKSCzboNdVkpiyWuGYIiHSEfws0kLCF8 chzShU2DJ6pkDIjzUykBG685eQ== X-Received: by 2002:a1c:9c85:: with SMTP id f127-v6mr1046143wme.73.1542186043440; Wed, 14 Nov 2018 01:00:43 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:4d39:8b22:d570:822a]) by smtp.gmail.com with ESMTPSA id n7-v6sm16951441wrt.60.2018.11.14.01.00.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Nov 2018 01:00:42 -0800 (PST) From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard , Benjamin Gaignard Subject: [PATCH v4 2/4] hwspinlock: add STM32 hwspinlock device Date: Wed, 14 Nov 2018 10:00:25 +0100 Message-Id: <20181114090027.7580-3-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181114090027.7580-1-benjamin.gaignard@linaro.org> References: <20181114090027.7580-1-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Benjamin Gaignard This patch adds support of hardware semaphores for stm32mp1 SoC. The hardware block provides 32 semaphores. Signed-off-by: Benjamin Gaignard Signed-off-by: Benjamin Gaignard --- version 4: - add Linaro SoB version 3 : - use postcore_initcall() instead of module_platform_driver() version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation - remove useless licence terms from header - fix alphabetic order issues - do not abort remove function if hwspin_lock_unregister() failed drivers/hwspinlock/Kconfig | 9 ++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/stm32_hwspinlock.c | 156 ++++++++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c -- 2.15.0 diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index e895d29500ee..7869c67e5b6b 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -49,6 +49,15 @@ config HWSPINLOCK_SPRD If unsure, say N. +config HWSPINLOCK_STM32 + tristate "STM32 Hardware Spinlock device" + depends on MACH_STM32MP157 + depends on HWSPINLOCK + help + Say y here to support the STM32 Hardware Spinlock device. + + If unsure, say N. + config HSEM_U8500 tristate "STE Hardware Semaphore functionality" depends on HWSPINLOCK diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index b87c01a506a4..ed053e3f02be 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SIRF) += sirf_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SPRD) += sprd_hwspinlock.o +obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c new file mode 100644 index 000000000000..34a8e009dc93 --- /dev/null +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics SA 2018 + * Author: Benjamin Gaignard for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hwspinlock_internal.h" + +#define STM32_MUTEX_COREID BIT(8) +#define STM32_MUTEX_LOCK_BIT BIT(31) +#define STM32_MUTEX_NUM_LOCKS 32 + +struct stm32_hwspinlock { + struct clk *clk; + struct hwspinlock_device bank; +}; + +static int stm32_hwspinlock_trylock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + u32 status; + + writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr); + status = readl(lock_addr); + + return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID); +} + +static void stm32_hwspinlock_unlock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + + writel(STM32_MUTEX_COREID, lock_addr); +} + +static const struct hwspinlock_ops stm32_hwspinlock_ops = { + .trylock = stm32_hwspinlock_trylock, + .unlock = stm32_hwspinlock_unlock, +}; + +static int stm32_hwspinlock_probe(struct platform_device *pdev) +{ + struct stm32_hwspinlock *hw; + void __iomem *io_base; + struct resource *res; + size_t array_size; + int i, ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io_base = devm_ioremap_resource(&pdev->dev, res); + if (!io_base) + return -ENOMEM; + + array_size = STM32_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); + hw = devm_kzalloc(&pdev->dev, sizeof(*hw) + array_size, GFP_KERNEL); + if (!hw) + return -ENOMEM; + + hw->clk = devm_clk_get(&pdev->dev, "hsem"); + if (IS_ERR(hw->clk)) + return PTR_ERR(hw->clk); + + for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++) + hw->bank.lock[i].priv = io_base + i * sizeof(u32); + + platform_set_drvdata(pdev, hw); + pm_runtime_enable(&pdev->dev); + + ret = hwspin_lock_register(&hw->bank, &pdev->dev, &stm32_hwspinlock_ops, + 0, STM32_MUTEX_NUM_LOCKS); + + if (ret) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int stm32_hwspinlock_remove(struct platform_device *pdev) +{ + struct stm32_hwspinlock *hw = platform_get_drvdata(pdev); + int ret; + + ret = hwspin_lock_unregister(&hw->bank); + if (ret) + dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev) +{ + struct stm32_hwspinlock *hw = dev_get_drvdata(dev); + + clk_disable_unprepare(hw->clk); + + return 0; +} + +static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev) +{ + struct stm32_hwspinlock *hw = dev_get_drvdata(dev); + + clk_prepare_enable(hw->clk); + + return 0; +} + +static const struct dev_pm_ops stm32_hwspinlock_pm_ops = { + SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend, + stm32_hwspinlock_runtime_resume, + NULL) +}; + +static const struct of_device_id stm32_hwpinlock_ids[] = { + { .compatible = "st,stm32-hwspinlock", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids); + +static struct platform_driver stm32_hwspinlock_driver = { + .probe = stm32_hwspinlock_probe, + .remove = stm32_hwspinlock_remove, + .driver = { + .name = "stm32_hwspinlock", + .of_match_table = stm32_hwpinlock_ids, + .pm = &stm32_hwspinlock_pm_ops, + }, +}; + +static int __init stm32_hwspinlock_init(void) +{ + return platform_driver_register(&stm32_hwspinlock_driver); +} +/* board init code might need to reserve hwspinlocks for predefined purposes */ +postcore_initcall(stm32_hwspinlock_init); + +static void __exit stm32_hwspinlock_exit(void) +{ + platform_driver_unregister(&stm32_hwspinlock_driver); +} +module_exit(stm32_hwspinlock_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs"); +MODULE_AUTHOR("Benjamin Gaignard ");