From patchwork Thu Nov 8 11:26:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 150500 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp702383ljp; Thu, 8 Nov 2018 03:26:27 -0800 (PST) X-Google-Smtp-Source: AJdET5fM3txNSvHJ8ibQhwY2scTmvJiEPH7E3CgHddK1xd5qxAkvX1d7CW+9QZCZ+8lv5ezUWTa4 X-Received: by 2002:a17:902:6b01:: with SMTP id o1-v6mr4203299plk.333.1541676387099; Thu, 08 Nov 2018 03:26:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541676387; cv=none; d=google.com; s=arc-20160816; b=OXndvmlV6bQ0kD2VzIQQLpBvN/leSPKgUReR+e1d9zU7PEONPZQVMEfOa3M2hQ9TsT uJeqiUE8mjOJRnchn5MAd0djcHzF3EZqQ+0orenGSbW+9bSkSAtA1anqhkQc/yRPtW8h Uctmn+08Z1lDZpkeg2rm2poF3eiCHAjsE7uHX+gw7Dl9Qsx560YS6treY4HoII6YhLLU veUO+2PI5KQPC+rW0WYSPYuYSCZhwwaCR+bhL72ibYlFshZOIUHngxZr8STiHI+Ge7YS 9/xHaBttYHO3Jsw9UNIzpQ7GwkOvqAzNov5QfjAnlKuB7JL9L+85vXdvgunucOw/C5R7 sRPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ZaCDbqqeU4pfmJT+OUqYCcslMwv/Lpkpl2OgyVASaLE=; b=l8D1BYg0c7tFL9eE+3Lgno/jrJv0UiPQNxwxgGDrn8jiV2d0QnT68B4NzChBCYBA1J 2RsGZayj0NkdR0dsGdBM4YujjC4IzDQrGRgToenpzEKr5dR0g1wS6CAWUO1UzZjSbBEV lXhfS0wX+8syL4X9pAiJqAEjm3c6kGbHa5Qu+ou1uBMyCzQao++TOZECo9X0s+HtPpAr QDGt+FFv+ywmrUTIftP8ck3LiDXc/Jo2EDWxeydsTbeDN+/RvesLu5iqVhVM+2J7lLZ3 hLIMdsut3DBf4EumYXpbGo0WzTF3aR/HgVq8zcImPisAa+0XUboRZPYyBP9/oJpGWOA+ vvmA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c3-v6si4030246pll.3.2018.11.08.03.26.26; Thu, 08 Nov 2018 03:26:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726659AbeKHVB2 (ORCPT + 6 others); Thu, 8 Nov 2018 16:01:28 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:53258 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbeKHVB2 (ORCPT ); Thu, 8 Nov 2018 16:01:28 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id wA8BQ1he003566; Thu, 8 Nov 2018 05:26:01 -0600 Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wA8BQ1P1038749 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Nov 2018 05:26:01 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 8 Nov 2018 05:26:00 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 8 Nov 2018 05:26:00 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wA8BPqhV011714; Thu, 8 Nov 2018 05:25:58 -0600 From: Vignesh R To: Tero Kristo , Rob Herring CC: Nishanth Menon , Mark Rutland , , , , Vignesh R Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add pinctrl regions Date: Thu, 8 Nov 2018 16:56:47 +0530 Message-ID: <20181108112647.7205-3-vigneshr@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108112647.7205-1-vigneshr@ti.com> References: <20181108112647.7205-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tero Kristo Add pinctrl regions for the main and wkup mmr. The range for main pinctrl region contains a gap at offset 0x2e4, and because of this, the pinctrl range is split into two sections. Signed-off-by: Tero Kristo Signed-off-by: Vignesh R --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + 3 files changed, 25 insertions(+) -- 2.19.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index adcd6341e40c..f7c2a60d5c80 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -69,4 +69,20 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c000 0x0 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinmux@11c2e8 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c2e8 0x0 0x24>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 8d7b47f9dfbf..19b46f40789b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -34,6 +34,14 @@ }; }; + wkup_pmx0: pinmux@4301c000 { + compatible = "pinctrl-single"; + reg = <0x4301c000 0x118>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + wkup_uart0: serial@42300000 { compatible = "ti,am654-uart"; reg = <0x42300000 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3d4bf369d030..873dca1d0813 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { model = "Texas Instruments K3 AM654 SoC";