From patchwork Thu Nov 8 11:26:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 150501 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp702527ljp; Thu, 8 Nov 2018 03:26:37 -0800 (PST) X-Google-Smtp-Source: AJdET5fgnJIhFf+obfI9fosT/NN6Ex2lKYqFjBa89K2qpxFDrwaQkGS/tgMhCnG76WVGFo+SMZOv X-Received: by 2002:a17:902:9897:: with SMTP id s23-v6mr4251938plp.229.1541676397727; Thu, 08 Nov 2018 03:26:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541676397; cv=none; d=google.com; s=arc-20160816; b=A+Afyi3kDHNOnKbIY1C3Scjq61/ox1vF7c6DnitsLjifSYZJHxZdMDoocoNJJYyFr5 L+ccvukl1OIYcT48EwqvMu/v7zHb8le2JmZHaXxCDqhcFG566/XNh/lSAUVq9wo8CLMi o/kneho6Q4MpLya8bXBFZjVhgw5m0XcCti5JV6vHTeJHlkx2IEDM4OIOVBgXDR9wTOpA W5rQ4Uw9Ks5Jyh/ApOJv5rluFW+f/DYIz67rN4/FQ8kLCV0akIX8KlEUr4/DV1W3vG0J gGLq58aJ50/e4mnfarO5vMgjbEGXYAHw4UKji8H/5dmBwj/8fb8gKu1rH2T6RzwSlwdg Tt1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bVIQo3ZWc1LkxowL3VZwE7p5BNrMzbAcQF5KeYBH/2A=; b=saKDC02fqANmfp4StnzIpjt6hXNxMysyOeBH+jbYzobVo3M8dGSbDuHZMgwYSkUwV6 8QS3PyTwBdAvXMrOG5c2UKWUyEN8mKwvfwCkopl4uE4bB2Z9xyFXjp2ufJUfSEfbd8cS 0BpCJ3o3BmkpuTfKeknc3Jp3mAbjzWKdBjB4U7xdoj1+LIkD8C8Nw1aYBHVAFEqYSYfE nW16mx7Sc2mBjcCofrtskcocV7KRsjXVZn1RZa0uxYAZ8Hfhg7xH6QnEZ1Co0payP6aX +XCuyT/4y829DbHHmmI2bLTh7eAmuhxfip/z1IJA7xasOrXi4JERof3gp9V93D/lkClx TVdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=m3jUOa9G; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c3-v6si4030246pll.3.2018.11.08.03.26.37; Thu, 08 Nov 2018 03:26:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=m3jUOa9G; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727223AbeKHVBj (ORCPT + 6 others); Thu, 8 Nov 2018 16:01:39 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:34046 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbeKHVBi (ORCPT ); Thu, 8 Nov 2018 16:01:38 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wA8BPwpw025662; Thu, 8 Nov 2018 05:25:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1541676358; bh=bVIQo3ZWc1LkxowL3VZwE7p5BNrMzbAcQF5KeYBH/2A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m3jUOa9GBRqjx9CAzPHE8GmbySlLmwut9G71bO/h8SIBd7z6nH5NQJ8OMu6Wo+nKI zVfyWwY/GEbgMfT/9kmVACQEoZxvWNxdyOO1sE+RhJIM+vVhRHPmsRxLFcQp4/zm/C bk2aWxypRiLysOMFU3a0hHJvaep3NDlkvgHPPeaw= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wA8BPwdW016521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Nov 2018 05:25:58 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 8 Nov 2018 05:25:58 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 8 Nov 2018 05:25:58 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wA8BPqhU011714; Thu, 8 Nov 2018 05:25:56 -0600 From: Vignesh R To: Tero Kristo , Rob Herring CC: Nishanth Menon , Mark Rutland , , , , Vignesh R Subject: [PATCH 1/2] dt-bindings: pinctrl: k3-am6: Introduce pinmux definitions Date: Thu, 8 Nov 2018 16:56:46 +0530 Message-ID: <20181108112647.7205-2-vigneshr@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108112647.7205-1-vigneshr@ti.com> References: <20181108112647.7205-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tero Kristo The dt-bindings header for TI K3-AM6 SoCs define a set of macros for defining pinmux configs in human readable form, instead of raw-coded hex values. Signed-off-by: Tero Kristo Signed-off-by: Lokesh Vutla Signed-off-by: Vignesh R --- MAINTAINERS | 1 + include/dt-bindings/pinctrl/k3-am6.h | 49 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 include/dt-bindings/pinctrl/k3-am6.h -- 2.19.1 diff --git a/MAINTAINERS b/MAINTAINERS index fb58c64dda49..7fd59955fd21 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2204,6 +2204,7 @@ S: Supported F: Documentation/devicetree/bindings/arm/ti/k3.txt F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* +F: include/dt-bindings/pinctrl/k3-am6.h ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE M: Santosh Shilimkar diff --git a/include/dt-bindings/pinctrl/k3-am6.h b/include/dt-bindings/pinctrl/k3-am6.h new file mode 100644 index 000000000000..42e22ee57600 --- /dev/null +++ b/include/dt-bindings/pinctrl/k3-am6.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for TI K3-AM6 pinctrl bindings. + * + * Copyright (C) 2018 Texas Instruments + */ +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM6_H +#define _DT_BINDINGS_PINCTRL_TI_K3_AM6_H + +/* K3 mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 +#define MUX_MODE15 15 + +#define PULL_DISABLE (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCTRL_200MHZ 0 +#define SLEWCTRL_150MHZ (1 << 19) +#define SLEWCTRL_100MHZ (2 << 19) +#define SLEWCTRL_50MHZ (3 << 19) +#define TX_DIS (1 << 21) +#define ISO_OVR (1 << 22) +#define ISO_BYPASS (1 << 23) +#define DS_EN (1 << 24) +#define DS_INPUT (1 << 25) +#define DS_FORCE_OUT_HIGH (1 << 26) +#define DS_PULL_UP_DOWN_EN 0 +#define DS_PULL_UP_DOWN_DIS (1 << 27) +#define DS_PULL_UP_SEL (1 << 28) +#define WAKEUP_ENABLE (1 << 29) + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +#define AM65X_IOPAD(pa, val) (((pa) & 0x1fff)) (val) +#define AM65X_WKUP_IOPAD(pa, val) (((pa) & 0x1fff)) (val) + +#endif