From patchwork Sat Nov 3 07:00:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 150090 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp259791ljp; Fri, 2 Nov 2018 23:56:30 -0700 (PDT) X-Google-Smtp-Source: AJdET5cnLHnEGiWyjvD/cOXcwSlCeuiPHD1sK/xjVp8HYlit/jRcEnnv+I/BWt5hujklu9Qn3zB3 X-Received: by 2002:a17:902:a416:: with SMTP id p22-v6mr5705161plq.284.1541228190540; Fri, 02 Nov 2018 23:56:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541228190; cv=none; d=google.com; s=arc-20160816; b=HbVrPvYbadCmrKyK1WP2qZ6r2Cx5TjBda95rUlprcMynMnMGu6w5I5UlqGxTdDpVdi JTKRKA/alajOGpUOBIcn12D1S7x4iA5Uc26kjd6IQ8xJvGq5EPY2Y2mkLZkcvqapuMsZ LoVxpPuX4vN5r+1pVEirJFmYTpCn+2l1iFrRAWhuU7aXAZd721oogYd+dLlQZ/57J55u 53/VjhMNGrY9OJH35s1AzmQ9PZLG6XBErdSpHYtMiDybePGHU5gxLDbqTNzZZbx9ZBp9 pgfgBxs0HQ3GCMaW8XmtV1QfYY/9to1hvPqloMIPiFxoOkaqeCY8Y+ERgVOtRKsna0ux JO9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=JfWafiBXzY3GqjbsFuSucku0AXH/F1fMBMNCXmqm9Bo=; b=yGUu/5cFozd2vD3SZLj0OyJ9SZEgLflaGpIYGxZVuuCzL5p7o8nyG7UzAv0O/l8632 lTTiLaKSP6SJ0dOWl784HeMwxRzv9w5SXcZOjSdXKFQEIrkiVilYEegGrH6QPP9ZT6VK ienRozrQXKNE5/Jt+ETnxIk4AJ1tEyKY+zndCmaKbvOWSABxCFNccZ98LXxS/3GoDFs1 4Yulwa9PMHM/dpT7x35TDF1Bn6gQdnBETwAfmt487s53KghHP9xHNtbOK4g0NI9oop6u gbaOS83knBDKFpW1TVcEY2hRy3pnocavI4FyUyASiLX5Alyv+Xb1E9+19kKvBkSEQt/4 tkrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jTIN85M0; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j10-v6si6994414pll.58.2018.11.02.23.56.29; Fri, 02 Nov 2018 23:56:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jTIN85M0; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726810AbeKCQGq (ORCPT + 6 others); Sat, 3 Nov 2018 12:06:46 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:37710 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726165AbeKCQGq (ORCPT ); Sat, 3 Nov 2018 12:06:46 -0400 Received: by mail-pg1-f195.google.com with SMTP id c10-v6so1926045pgq.4 for ; Fri, 02 Nov 2018 23:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=JfWafiBXzY3GqjbsFuSucku0AXH/F1fMBMNCXmqm9Bo=; b=jTIN85M0e6ssJS2pgY1mxXpIKlMwc/fumm323nDFfbO/lCC1UUFxjEp5KYImaWgEOJ urXdZiihu3RvQY8NwT6UeoQowWffDDKqbsavC6nGiVU0j8MRAgipxxslaZiRdCPA9YuQ HSjUj54e6DdBAelP9paOtaX1lHbBAQvAazd0M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=JfWafiBXzY3GqjbsFuSucku0AXH/F1fMBMNCXmqm9Bo=; b=CA4e5p/dzBNIoRt9Y8yCHOkowjVQFg9JoFsKbhkK6rozT+TN6w8N/EhJIHLN5HUMXr yS6jNHIMcWTPTdBbP0Zztg3JLcXItMybRvECAkRnF3TTwwghWFFAiq5UiBVFN+6JTlxm 7GhRy+AO/gm2SPtaiAce/cjph8pbOeESShF8H/2tKWYjBVmLWZKDTsWq+dlHZS/cqUD8 rrGOuvnptVNLSPX7VejQ9EYueuyHnqnqGhqut/q8gJY5oP1d/1TE43ZjONxTwUDLEIbE sEe7U3GxRRaLMBXPfEojj7dpj6W667NhxAa/nen4mXQN8NT6HV1kDMWjwJ1WRaYiaapR DPAg== X-Gm-Message-State: AGRZ1gKPvDsXhs0qaAaoWLDl2QvjnoMxQdqWJoURbClgPXEXqvBgs6cl d/lB2JmZVRHiqZjp8Un46sWEPA== X-Received: by 2002:a62:9f90:: with SMTP id v16-v6mr14603111pfk.207.1541228187577; Fri, 02 Nov 2018 23:56:27 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id p64-v6sm36254870pfi.22.2018.11.02.23.56.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Nov 2018 23:56:26 -0700 (PDT) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Subject: [PATCH] clk: qcom: smd: Add support for QCS404 rpm clocks Date: Sat, 3 Nov 2018 00:00:02 -0700 Message-Id: <20181103070002.19106-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Taniya Das Add rpm smd clocks, PMIC and bus clocks which are required on QCS404 for clients to vote on. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan [bjorn: Dropped cxo, voter clocks and static initialization] Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + drivers/clk/qcom/clk-smd-rpm.c | 45 +++++++++++++++++++ include/dt-bindings/clock/qcom,rpmcc.h | 4 ++ 3 files changed, 50 insertions(+) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 4491d1c104aa..87b4949e9bc8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" + "qcom,rpmcc-qcs404", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 850c02a52248..d3aadaeb2903 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -611,10 +611,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; +/* QCS404 */ +DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); + +DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); + +DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); + +DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8); + +static struct clk_smd_rpm *qcs404_clks[] = { + [RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk, + [RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, + [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, + [RPM_SMD_CE1_CLK] = &qcs404_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk, + [RPM_SMD_RF_CLK1] = &qcs404_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a, + [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk, +}; + +static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { + .clks = qcs404_clks, + .num_clks = ARRAY_SIZE(qcs404_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, + { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index c585b82b9c05..3658b0c14966 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -123,5 +123,9 @@ #define RPM_SMD_DIV_A_CLK3 73 #define RPM_SMD_LN_BB_CLK 74 #define RPM_SMD_LN_BB_A_CLK 75 +#define RPM_SMD_BIMC_GPU_CLK 76 +#define RPM_SMD_BIMC_GPU_A_CLK 77 +#define RPM_SMD_QPIC_CLK 78 +#define RPM_SMD_QPIC_CLK_A 79 #endif