From patchwork Wed Oct 31 09:30:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 149771 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6552640ljp; Wed, 31 Oct 2018 02:30:54 -0700 (PDT) X-Google-Smtp-Source: AJdET5cbCIoiiZPF487bu9+vWIac48EaEyxbnqmUyK3JAx4gYKiLGxYMrSkKqQExajjg2YABE7kD X-Received: by 2002:a17:902:9a44:: with SMTP id x4-v6mr2513520plv.121.1540978254697; Wed, 31 Oct 2018 02:30:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540978254; cv=none; d=google.com; s=arc-20160816; b=PzmH93IPL+baCSOEWhnmCtuTDsKxUo+nGjhGLYXfd/0B5K5eLTZ08GhV8W+BrVesYI DcB3LTS6nK/6IKMNsVW07VJ3zF2gNbKld5YVKfY68L92YywT/TGi4GR+MAUdBNrVlMee zND/77vyTANwTm9g5F1aAUDMBI2OoS7RNXSKdcvH1VFVxl+GJXgVQIZgKRI4i3VAUSLL GHna+Jj2GE5CBoOZic+lSaD57wi8+hOwD5EwYixfji9odAMxVT2G5rL8rXot/3JcGjhb Xy4MgGgnLa3zw56muXMvX50196BecvJGH5eeXVOFgfqVOAEKKK1H2aG4i4SRQKu1qvxA hodg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ZKXzc/9xi2oqrkPABloEIrBfH+ajRu+w1WHKhdOM4Rk=; b=AR3ql1eDyFrwk79+MObrszuMep+7/f3qSp7tYicihu5PPlhm1dKhA0sj6KHSKoBXrW zSMcTVIuaniW5rnwjBmXoNVuRO59fazu1Nx4nOQbqSRUb0MTVLzmlHdW6HwnJ3vJyDkU 7rAtEASY0OBaCDgiZp5UJu1NhWTOiabl6agql5y7UquM2Ar9P0BXo08ZD+dmFPljSDx+ rjtUp9rw49FRDt23TqVauE8VxowVWFGx5b3a+oXxZeHbHfcY7RqQ0pLSIp/HzZ0O4ldY pF6VDdHH+0VTpV81PxgSqOgffJlafjEPRwAB1Aub93dm4pTyKw18fZBgYDOeDMtzXgb1 OBCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aan0EMnX; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m12-v6si26006136pll.105.2018.10.31.02.30.54; Wed, 31 Oct 2018 02:30:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aan0EMnX; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728087AbeJaS2M (ORCPT + 6 others); Wed, 31 Oct 2018 14:28:12 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:43482 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727597AbeJaS2L (ORCPT ); Wed, 31 Oct 2018 14:28:11 -0400 Received: by mail-wr1-f65.google.com with SMTP id t10-v6so15626924wrn.10 for ; Wed, 31 Oct 2018 02:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZKXzc/9xi2oqrkPABloEIrBfH+ajRu+w1WHKhdOM4Rk=; b=aan0EMnXfDfOU3ca4R0bzQftvlM4ux2NUaP9DsCSp15jp64rmSsQvkALE+o9L+aXNj NTBE2ziWR+VhvyST0Upny13wP0AL3yUYufEUy+qscRzayHjwqqJCrFx+2ZI7w+XZik8h OQKLeLjjRSWHFGdJSu8tczyhIjt85xRHN5Dsk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZKXzc/9xi2oqrkPABloEIrBfH+ajRu+w1WHKhdOM4Rk=; b=YOfrDFnwaBto8GhWQeC2M/qRljztrqNY3bL8Yzm88IPOdKaI6LSVwEkwBG+tJfvLgL h+CyFs2S/YYceJTdRKi6AxUN+tGc/7mJ+dsf9r/POOMDdcN4amBetHjpO9oOMdIuf9Gj GSv4/B5S+jQsHUp0z3rn/ZjsrFby5XkmMW2EpIQlKu7ed7Y9CnFtiMQ2ksUeMkFw1gif fNTEgjo7Z+/J1wJA34lWWXUj+iursrEKLCkqZnwmpt2dqJHP2vODLzzjmciwPBTiPvkm 7wBTpCH4FfD19MoYeVpXSoy5COrtXzhNc403Uzbbo9wpTy8STP9x6SYoCWxPy6jEYfL7 maEA== X-Gm-Message-State: AGRZ1gL5b3K4rua840mr71Fh2ieT0OzO4bPHgZwA1eCiXYP465CdaeXr krau1uZD4cCWCLGhqIcbPLiv4Q== X-Received: by 2002:adf:e485:: with SMTP id i5-v6mr1953416wrm.101.1540978250250; Wed, 31 Oct 2018 02:30:50 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1086:999:fd1b:8629:a7fc:68b]) by smtp.gmail.com with ESMTPSA id w14-v6sm10737377wrt.73.2018.10.31.02.30.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Oct 2018 02:30:49 -0700 (PDT) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH 1/5] dt-bindings: hwlock: Document STM32 hwspinlock bindings Date: Wed, 31 Oct 2018 10:30:28 +0100 Message-Id: <20181031093032.20386-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181031093032.20386-1-benjamin.gaignard@st.com> References: <20181031093032.20386-1-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings for STM32 hardware spinlock device Signed-off-by: Benjamin Gaignard --- .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt -- 2.15.0 diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt new file mode 100644 index 000000000000..7a999479d802 --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -0,0 +1,23 @@ +STM32 Hardware Spinlock Device Binding +------------------------------------- + +Required properties : +- compatible : should be "st,stm32-hwspinlock". +- reg : the register address of hwspinlock. +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. +- clock-names : Must contain "hwspinlock". +- clocks : Must contain a phandle entry for the clock in clock-names, see the + common clock bindings. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hwspinlock"; + };