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[209.132.180.67]) by mx.google.com with ESMTP id s17-v6si26258302pge.99.2018.09.21.03.26.13; Fri, 21 Sep 2018 03:26:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bxhKx+6y; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390488AbeIUQOZ (ORCPT + 6 others); Fri, 21 Sep 2018 12:14:25 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54720 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQOY (ORCPT ); Fri, 21 Sep 2018 12:14:24 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LANnA1032939; Fri, 21 Sep 2018 05:23:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525429; bh=oDF6ndAYJvQk5lqs0pyCrinasCIrID1DOTXjY2ayVww=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bxhKx+6y89OzMZGYuHtzWPoV5lsR1NRkqPJTDy6pzxhxSt8B60pbKD93LOfvQaq4m 3nWggHxBSbjAoR7kd7TMXv75vOkeZu1xGk+cbpae7kfJU0jSne+Dxb9FU2KEty4GXJ 7qbDt5XdprYqDR238FiAsGpGwuMkPYXtKNAl03qw= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LANn7P018958; Fri, 21 Sep 2018 05:23:49 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:48 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:48 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtN032280; Fri, 21 Sep 2018 05:23:44 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 19/40] PCI: keystone: Cleanup set_dbi_mode and get_dbi_mode Date: Fri, 21 Sep 2018 15:51:34 +0530 Message-ID: <20180921102155.22839-20-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Use BIT() macro for DBI_CS2 and cleanup set_dbimode and get_dbi_mode Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d5304c4a1eb5..728b1e0db314 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -40,7 +40,7 @@ #define LTSSM_EN_VAL BIT(0) #define LTSSM_STATE_MASK 0x1f #define LTSSM_STATE_L0 0x11 -#define DBI_CS2_EN_VAL 0x20 +#define DBI_CS2 BIT(5) #define OB_XLAT_EN_VAL BIT(1) /* Application registers */ @@ -214,11 +214,12 @@ static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) u32 val; val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); + val |= DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); do { val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (!(val & DBI_CS2_EN_VAL)); + } while (!(val & DBI_CS2)); } /** @@ -232,11 +233,12 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) u32 val; val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); + val &= ~DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); do { val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (val & DBI_CS2_EN_VAL); + } while (val & DBI_CS2); } static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,