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[209.132.180.67]) by mx.google.com with ESMTP id t71-v6si1571830pgd.352.2018.09.21.03.22.49; Fri, 21 Sep 2018 03:22:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="bUPipoG/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727681AbeIUQK7 (ORCPT + 6 others); Fri, 21 Sep 2018 12:10:59 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34914 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727392AbeIUQK7 (ORCPT ); Fri, 21 Sep 2018 12:10:59 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMOfM030289; Fri, 21 Sep 2018 05:22:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525344; bh=iBGFjwERlyNXfssV0mhi5P70SxiWNRCvnKhKGvOqAU0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bUPipoG/GPtwq55FxNqNDgbtTZGWgFlGmC9ZtO9hZw4DmQYrDP7V902xkJZuDL/N8 OUF/vqYlzPuYnWyHaNM+RBfPJtxLEDU2X4a8+XULSZykyhkBFvNoWSOBJEyDtAEOn+ SVTefYQGlUn6r04YzUAHQQZYEixLhoM9T39gt1Lo= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMOv4017403; Fri, 21 Sep 2018 05:22:24 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:24 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:24 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEt5032280; Fri, 21 Sep 2018 05:22:20 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 01/40] PCI: keystone: Use quirk to limit MRRS for K2G Date: Fri, 21 Sep 2018 15:51:16 +0530 Message-ID: <20180921102155.22839-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PCI controller in K2G also has a limitation that memory read request size (MRRS) must not exceed 256 bytes. Use the quirk to limit MRRS (added for K2HK, K2L and K2E) for K2G as well. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e88bd221fffe..7d43e10a03b0 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -36,6 +36,7 @@ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 #define PCIE_RC_K2L 0xb00a +#define PCIE_RC_K2G 0xb00b #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) @@ -50,6 +51,8 @@ static void quirk_limit_mrrs(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, { 0, }, };