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[209.132.180.67]) by mx.google.com with ESMTP id f2-v6si23235512pgg.552.2018.09.20.23.01.20; Thu, 20 Sep 2018 23:01:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G6RWy3YR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389250AbeIULsg (ORCPT + 6 others); Fri, 21 Sep 2018 07:48:36 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:33376 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389231AbeIULsf (ORCPT ); Fri, 21 Sep 2018 07:48:35 -0400 Received: by mail-io1-f68.google.com with SMTP id r196-v6so11098309iod.0 for ; Thu, 20 Sep 2018 23:01:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HWT3twxDE9rajVaHTUWulfxI8G27u4GTCDXe+LGxpPw=; b=G6RWy3YRam/B/N4P3ZwsDol/oMhyEvNrMHCB/0oz+rqJ67JVLAaywTclNxR38L7Khp Pw1ysQ2VJp1W+kgEsoNoj9fHR4w49aK51uQM++PW71jRG9r6Rd3EeQf6dFljxTeswUln dfEKGRegRr5m32H5UEfwCPQWac1itNgmhFR5g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HWT3twxDE9rajVaHTUWulfxI8G27u4GTCDXe+LGxpPw=; b=Ij26kW9pG9XPHIMoIbac4IR2iairOgiuzngEiN05GMIX8QELttj15eVnuuryki+/dE 9JYA+7YmZ0t+sMJJBNJJZY2OBR47v7g8gOcBgVNzcN3G/7Dm547yOmWJgzf9SBoA1w88 6jZR7xblXPpfINEJ0SWvplBZ/swQMGsJO/09PhUNcNf6HdFpAg7aOqcoUEtZhfxTyFre paK79cddR2qglNIEBm5ULl8MRURGFzteBDL6euC88LxkaYu+6hlcdjGCDkB+bIWvn6r/ FypfPn/x1g5wvexpAAF8q5b/OdQ1NHkXQyfKOXylgYK/xvARBC8G9RbUK/mulE0yBoh0 a6sw== X-Gm-Message-State: APzg51Bcth51ahMbvPFzCwOfB3e45FHA1yjmb3VGGFRALvLR8qTl2PR4 IthfiLzvncw9RjVho8QDKgxB X-Received: by 2002:a6b:2495:: with SMTP id k143-v6mr31079959iok.122.1537509678073; Thu, 20 Sep 2018 23:01:18 -0700 (PDT) Received: from localhost.localdomain ([209.82.80.116]) by smtp.gmail.com with ESMTPSA id b195-v6sm1973875itc.42.2018.09.20.23.01.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Sep 2018 23:01:17 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kucheria@linaro.org, linux-clk@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/4] arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC Date: Thu, 20 Sep 2018 23:01:01 -0700 Message-Id: <20180921060103.21370-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921060103.21370-1-manivannan.sadhasivam@linaro.org> References: <20180921060103.21370-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add clock nodes for HiSilicon Hi3670 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 43 +++++++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index c90e6f6a34ec..8a0ee4b08886 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -7,6 +7,7 @@ */ #include +#include / { compatible = "hisilicon,hi3670"; @@ -144,6 +145,48 @@ #size-cells = <2>; ranges; + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3670-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; + }; + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3670-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x1000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3670-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3670-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3670-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + }; + + media1_crg: media1_crgctrl@e87ff000 { + compatible = "hisilicon,hi3670-media1-crg", "syscon"; + reg = <0x0 0xe87ff000 0x0 0x1000>; + #clock-cells = <1>; + }; + + media2_crg: media2_crgctrl@e8900000 { + compatible = "hisilicon,hi3670-media2-crg","syscon"; + reg = <0x0 0xe8900000 0x0 0x1000>; + #clock-cells = <1>; + }; + uart6_clk: clk_19_2M { compatible = "fixed-clock"; #clock-cells = <0>;