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[209.132.180.67]) by mx.google.com with ESMTP id 194-v6si13066959pgf.651.2018.07.31.20.40.03; Tue, 31 Jul 2018 20:40:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=R5+DXHo8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731682AbeHAFXU (ORCPT + 5 others); Wed, 1 Aug 2018 01:23:20 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:37792 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730957AbeHAFXU (ORCPT ); Wed, 1 Aug 2018 01:23:20 -0400 Received: by mail-pl0-f67.google.com with SMTP id d5-v6so2560021pll.4 for ; Tue, 31 Jul 2018 20:39:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y2Xim6wZcJhjsafQ7hCOBFR4DJdA4YrNANwR9AoDSRg=; b=R5+DXHo8bfJAG+6yqGLz4bsROhYHFYVXz78bAOjEscpMxI2J91pWNCSwF7WE3HCUZo b2IymvEjrr9wKZiL9MnT2smndkkxaOUF1vstW2Bcd127nxnclKiqqXDbl6MTuyOXbilc l9lli/NM292mNTBoePfbc2S27whW1+ur9odyM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y2Xim6wZcJhjsafQ7hCOBFR4DJdA4YrNANwR9AoDSRg=; b=OsAAo09vik64LH0mz7Q21lYIXXV3g/OeqV25Cl9kcunjTujB//gSQvfGRNreAXqITP ywO9K0PJjpa0+m9SiyWym5DqqjjzloIWj+ib9yBgwii6j/wIRcE/OFckQnfGo5RpQN+E wfzLjcwqFlv2TxJYJ6ZrZi3rnUooLbp+f9JI5PQySRD+SBsFz6C8dHvWEBTIpGcn4CRy r/M3NXZsZONTZ2w3RyR5Ok8bEHEdO6yNcVKNdd1CSYXh7jGE2hkiNbEUOgB0K+qgNjbE 4vUEn7ZRSNkfJz+ePsHPaR61wVq14V0Vzna9eC5ymUXd4rBFTSj/jM/MNKzs8wmPoVsb WMTA== X-Gm-Message-State: AOUpUlFUYV3Esr5e7qRbLWpOWVpxX6TeGq0XquMXlnJjpgSesn75D/sU Ok/x8pIc52O5twJyNc7Sn6++ X-Received: by 2002:a17:902:760d:: with SMTP id k13-v6mr22703733pll.56.1533094793555; Tue, 31 Jul 2018 20:39:53 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730e:f0ae:ac4e:9cdd:28a2:4bf9]) by smtp.gmail.com with ESMTPSA id d19-v6sm34879545pgi.50.2018.07.31.20.39.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Jul 2018 20:39:52 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, lee.jones@linaro.org, arnd@arndb.de Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 01/10] dt-bindings: clock: Add syscon support to Actions Semi Owl SoCs Date: Wed, 1 Aug 2018 09:09:06 +0530 Message-Id: <20180801033915.15880-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> References: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since the clock and reset management units are sharing the same memory map, document the clock bindings to support System Controller. Signed-off-by: Manivannan Sadhasivam --- .../bindings/clock/actions,owl-cmu.txt | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt index d1e60d297387..649c95fc4582 100644 --- a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt +++ b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt @@ -9,8 +9,6 @@ Required Properties: - compatible: should be one of the following, "actions,s900-cmu" "actions,s700-cmu" -- reg: physical base address of the controller and length of memory mapped - region. - clocks: Reference to the parent clocks ("hosc", "losc") - #clock-cells: should be 1. @@ -21,6 +19,13 @@ All available clocks are defined as preprocessor macros in corresponding dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be used in device tree sources. +The CMU registers are part of the system-controller block on Owl SoCs. + +Parent node should have the following properties : +- compatible: "syscon", "simple-mfd" +- reg: physical base address of the controller and length of memory mapped + region. + External clocks: The hosc clock used as input for the plls is generated outside the SoC. It is @@ -31,11 +36,15 @@ Actions Semi S900 CMU also requires one more clock: Example: Clock Management Unit node: - cmu: clock-controller@e0160000 { - compatible = "actions,s900-cmu"; + sysctrl: system-controller@e0160000 { + compatible = "syscon", "simple-mfd"; reg = <0x0 0xe0160000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; + + cmu: clock-controller { + compatible = "actions,s900-cmu"; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; }; Example: UART controller node that consumes clock generated by the clock