From patchwork Fri Apr 27 11:47:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 134593 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp618048lji; Fri, 27 Apr 2018 04:48:30 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpa18QV3dRcenF/EiwgVIu8wieoI4QpwOBG2erAuxy0eGba/VqZOWZZgRIvpDm0FYKIQcnR X-Received: by 2002:a63:7443:: with SMTP id e3-v6mr1849389pgn.369.1524829710831; Fri, 27 Apr 2018 04:48:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524829710; cv=none; d=google.com; s=arc-20160816; b=AjUqo1rm3zD36G1ghFQ4nvkpT7ir13iHLp7QWzYh+P8dDFQJthZn1u9w4x9SNAF8kb tmEUURglj3jbdnlIOpBxkWRd6PTRVlhGeub52YIlMTGjn/Nu8QZwRbm+bsnjA3oqvC1Y DK2OvAnSE2cyit6HuFvnzgcOwAEkF8AJ72+43EAdSvp9jELjkw/qrAF70+pcnrDnE379 CH1jTzNif6voWDKyCVk7VOZ3pKijsvBFUc2lQz3XtV0T3x9F5uPlozYhU6isCu1ypCuZ poZWMLul5Sx3ti09bNGe3sCjkVIqNm9K/23/XHMraxWCOlMPmCc0jUiOTMhQBLejUzSR REbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=VR5Q5T5/C2MBsCsgzwHe/hitYr5Nv5+LkY2Qc7oWUrg=; b=px6gzU5xeKYSqWw/J0pd18KqHM7oo0xyCFkaWlfgl73Mzzz24UfNm3dmvHnEXJGVd7 7hme//5UTMWU3ksT0kj65YFE7i4sYQk+eL7on0QKfTOo8zPQfLukAiSLXuMFtPmmanVa U7lqrj7OPIucPx9ncSdMIZTaDz+VjKwhJc6RLLEqPNkzjUi/VZMNo3rQD2Luq10kMT2j RlEH55QzF84L55AcUhDMyaAXg6pkixCIrX86WRt5ndf8/fwcuFDtRt99O/S3R/lxZUBJ oJCGFKGZ8GX6CA+vQl2i53r1O9y20tnd+NAKPgjUvxthsFGb1nIzMnEKWfcOM2rpvpOD 5aKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jBefi7qs; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h3-v6si1138333pld.137.2018.04.27.04.48.30; Fri, 27 Apr 2018 04:48:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jBefi7qs; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758161AbeD0Ls2 (ORCPT + 6 others); Fri, 27 Apr 2018 07:48:28 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:61748 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758151AbeD0LsU (ORCPT ); Fri, 27 Apr 2018 07:48:20 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3RBmEC7002373; Fri, 27 Apr 2018 06:48:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524829694; bh=NFBabPHv0STdBAP28nM1CMtlVlFOc2W9SkWwtHoKEcw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jBefi7qsimX4Gv9esbMU4Yqu+/QmA/wZe4PMTmfajeCndrBmk45SWGy/wCnUjPqDP 8nw9qKW6cTYF4zoBiyjsokOyNpcOd16P8y7hrzzO31k0YoCnbeE3fDglDhUeIzxE/S VJYb+AD+1A37LbEcp+2oAE4JbFkcz5fW61J7cakE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RBmEKW021525; Fri, 27 Apr 2018 06:48:14 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 06:48:13 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 06:48:13 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RBlRSS014207; Fri, 27 Apr 2018 06:48:11 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Adrian Hunter CC: Rob Herring , Mark Rutland , , , , , Subject: [PATCH v5 14/14] mmc: sdhci-omap: Get IODelay values for 3.3v DDR mode Date: Fri, 27 Apr 2018 17:17:23 +0530 Message-ID: <20180427114723.2687-15-kishon@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427114723.2687-1-kishon@ti.com> References: <20180427114723.2687-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org commit 8d20b2eae6c47b095523 ("mmc: sdhci_omap: Add support to set IODELAY values") stored IODelay values for all MM/SD modes in pinctrl_state structure member of sdhci_omap_host. However for DDR mode it gets IODelay values only for 1.8v DDR mode. Since some of the platforms which uses sdhci-omap has IO lines connected to 3.3v, get IODelay values for 3.3v DDR mode. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci-omap.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.17.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index bd5e03d177e0..f3a7c8ece4be 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -842,8 +842,15 @@ static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps, MMC_CAP_1_8V_DDR); - if (!IS_ERR(state)) + if (!IS_ERR(state)) { pinctrl_state[MMC_TIMING_MMC_DDR52] = state; + } else { + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v", + caps, + MMC_CAP_3_3V_DDR); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_MMC_DDR52] = state; + } state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, MMC_CAP_SD_HIGHSPEED);