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[209.132.180.67]) by mx.google.com with ESMTP id d4si4392489plo.114.2017.12.14.22.25.23; Thu, 14 Dec 2017 22:25:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=tPlFAFiZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753173AbdLOGZU (ORCPT + 6 others); Fri, 15 Dec 2017 01:25:20 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:42852 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753123AbdLOGZQ (ORCPT ); Fri, 15 Dec 2017 01:25:16 -0500 Received: by mail-pf0-f194.google.com with SMTP id d23so5483527pfe.9; Thu, 14 Dec 2017 22:25:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=shjmyMylXZHOqCOBFulA4kCeoeosK1EP6VqEWYDZ7gw=; b=tPlFAFiZpghbKd+KqezhLcFJWzW6y7gH6gnBuqYzjYZW0zaIO2QayEzVhdyB3YdzDO BxIcIxMqkkTTV52wAAAMJ6AcmDmjj4dc12shkboASeNTe26AaKCmKBFMbEyUOlITbOYM WLz+aYEAKwLuhEWLWcUlg3yKgwjL0fNz54a+OfXa64MqBg5D7bkfZEtocY+i47TuL9vE J6BXpukENOYk8BhtVpdky0yIDE1atFyh7H4cngt9RyFdW8v+qToruyNiVtH3qybckQgv NoEV43wfILbjQX+5sgjarl4e23EbkQro7hweG1tjSC2xz2rNvyyRqDcNk9K2jkCip+Tj A83g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=shjmyMylXZHOqCOBFulA4kCeoeosK1EP6VqEWYDZ7gw=; b=cwEnz7H/9GKfn/2kY2YQOeDcwP06BWV6OZi4bNK9s069LPyoDLo5n8EnhLn1lkzfUi kF5JRDjKXoBDKYH4hWqKncUlqJQMPvclx5S7jkrVF7A61YetepLA0VAINnFvDo8sgdG/ bLac4p1OwWaZLI/ym3M4Fz8JzLmODRfKSHlyaQ0yU/Xm+Wb9wQ8bILzLmWWs6I3O/LeB gMngyRBARdRLwKEJcKGQXWJweu8V2qCaRK9RHktEegIv8Io7YsPKw6tQM/c9aDok/eA4 oMhznKd10Qa0IV9v8DGhwDR0oUnAL8c8Zl3o7gLg4sOOmD54TCDFICJdXTYbeq8kdYun Vx0g== X-Gm-Message-State: AKGB3mIQYizSxBpTJAGSHWGIM3+vxnhVkhj7F9PYwXB06osLFepr5JXp 8IkYaW2x8L6HxpsHzHaaU50= X-Received: by 10.84.242.76 with SMTP id c12mr12284226pll.445.1513319115235; Thu, 14 Dec 2017 22:25:15 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id q9sm12224780pfl.116.2017.12.14.22.25.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Dec 2017 22:25:13 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 15 Dec 2017 16:55:05 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Arnd Bergmann , Andrew Jeffery , Patrick Venture , Xo Wang , Lei YU Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Benjamin Herrenschmidt , Jeremy Kerr , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v2 01/19] dt-bindings: clock: Add ASPEED constants Date: Fri, 15 Dec 2017 16:54:25 +1030 Message-Id: <20171215062443.23059-2-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171215062443.23059-1-joel@jms.id.au> References: <20171215062443.23059-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These will be merged as part of the clock driver. This commit is included so the tree will build without the clock series being applied. Signed-off-by: Joel Stanley --- v2: - remove NUM_CLKS define. There's no need for it to be part of ABI --- include/dt-bindings/clock/aspeed-clock.h | 52 ++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Rob Herring diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 000000000000..d3558d897a4d --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef DT_BINDINGS_ASPEED_CLOCK_H +#define DT_BINDINGS_ASPEED_CLOCK_H + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 + +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + +#endif