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[209.132.180.67]) by mx.google.com with ESMTP id s19si8807466pfj.225.2017.10.12.11.33.08; Thu, 12 Oct 2017 11:33:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RO6N56OA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753219AbdJLSdH (ORCPT + 6 others); Thu, 12 Oct 2017 14:33:07 -0400 Received: from mail-wm0-f54.google.com ([74.125.82.54]:52226 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751900AbdJLSdF (ORCPT ); Thu, 12 Oct 2017 14:33:05 -0400 Received: by mail-wm0-f54.google.com with SMTP id k4so15741482wmc.1 for ; Thu, 12 Oct 2017 11:33:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6UJEeZLBbhQX13SJYZB/zIdzNpC/DSaYF7tRQvJrMdQ=; b=RO6N56OAC29g5wF6WHfq7JT5ur4I0J8DucGTPDbWZcocYLUYOXU6NVddzUC0muuumB IW4wmulNoUAC8DGRpFius+CngmRnUuA9fisRRpo6Xa8W0qI7NlPG6/bVdlev2hd8kag9 pPMNTCBOC3MPAulPgpQvZ+oteJ35OObhod6SI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6UJEeZLBbhQX13SJYZB/zIdzNpC/DSaYF7tRQvJrMdQ=; b=Y51UA6IXAvKj1u1eBbdIE2KVT9fVQ5dFqdQsqFM62eG09uUDmlZpN1fxKaKP45QpqO QZdUp8SPfZQ7bBJcmQP/qWncgIcT0samAP7yDACdmd4DkmQicOlXk10bqfDMLsBX2HXe x/IX3RODkWzuCYsm10QL6RNWclvriBqZ47Jgrgq5da7tNPA24IIOxa/+pIkTMoPKMpEm lwXWQeQryqp/BegGt0DElVaNNjGMV2PiYXeuRCAhogffl8MdLRQCn56CHAQcoOAG1EmB 0Fi3rjxg5ebRsc4iFzQDKEKbC8BtSBFxJ+1Hqg6Llr3cs3IE4JRlLhvEBzKk8oas2uNK 7EGA== X-Gm-Message-State: AMCzsaUuPSrgiUEes6sCag6zXD6nx5VXqZGHyqeEz1J/QadwLyM5sh7F EfRHPBBVYcy0o8fWMlfeLhtfFA== X-Google-Smtp-Source: AOwi7QDvIVF2JemxDDq5JzmhNlxYYuQHNiX3F5sKQ18lGyzIJQePw3Iqx6z16G7821w+jVukEl73cQ== X-Received: by 10.223.128.170 with SMTP id 39mr2817412wrl.236.1507833183801; Thu, 12 Oct 2017 11:33:03 -0700 (PDT) Received: from localhost.localdomain ([196.78.24.219]) by smtp.gmail.com with ESMTPSA id i13sm14730579wre.93.2017.10.12.11.33.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Oct 2017 11:33:03 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v3 2/2] drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Date: Thu, 12 Oct 2017 19:32:47 +0100 Message-Id: <20171012183247.23679-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171012183247.23679-1-ard.biesheuvel@linaro.org> References: <20171012183247.23679-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 ++ arch/arm64/Kconfig | 8 +++ drivers/irqchip/irq-gic-v3-its.c | 63 +++++++++++++++++++- 3 files changed, 72 insertions(+), 3 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cdab0ea5..0798a61bbf99 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional: +- socionext,synquacer-pre-its: (u32, u32) tuple describing the host address + and size of the pre-ITS window, as implemented on the Socionext Synquacer SoC + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..c4361dff2b74 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. endmenu diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 891de07fd4cc..2fc4fba0cc4c 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -97,12 +97,18 @@ struct its_node { struct its_cmd_block *cmd_write; struct its_baser tables[GITS_BASER_NR_REGS]; struct its_collection *collections; + struct fwnode_handle *fwnode_handle; struct list_head its_device_list; u64 flags; u32 ite_size; u32 device_ids; int numa_node; + unsigned int msi_domain_flag_mask; bool is_v4; + + /* for Socionext Synquacer pre-ITS */ + u32 pre_its_base; + u32 pre_its_size; }; #define ITS_ITT_ALIGN SZ_256 @@ -1095,14 +1101,29 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, return IRQ_SET_MASK_OK_DONE; } +static u64 its_irq_get_msi_base(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + + if (unlikely(its->pre_its_size > 0)) + /* + * The Socionext Synquacer SoC has a so-called 'pre-ITS', + * which maps 32-bit writes targeted at a separate window of + * size '4 << device_id_bits' onto writes to GITS_TRANSLATER + * with device ID taken from bits [device_id_bits + 1:2] of + * the window offset. + */ + return its->pre_its_base + (its_dev->device_id << 2); + + return its->phys_base + GITS_TRANSLATER; +} + static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); - struct its_node *its; u64 addr; - its = its_dev->its; - addr = its->phys_base + GITS_TRANSLATER; + addr = its_irq_get_msi_base(its_dev); msg->address_lo = lower_32_bits(addr); msg->address_hi = upper_32_bits(addr); @@ -2752,6 +2773,27 @@ static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) its->ite_size = 16; } +static void __maybe_unused its_enable_quirk_socionext_synquacer(void *data) +{ + struct its_node *its = data; + u32 pre_its_window[2]; + u32 ids; + + if (!fwnode_property_read_u32_array(its->fwnode_handle, + "socionext,synquacer-pre-its", + pre_its_window, + ARRAY_SIZE(pre_its_window))) { + its->pre_its_base = pre_its_window[0]; + its->pre_its_size = pre_its_window[1]; + + ids = ilog2(its->pre_its_size) - 2; + if (its->device_ids > ids) + its->device_ids = ids; + + its->msi_domain_flag_mask = ~IRQ_DOMAIN_FLAG_MSI_REMAP; + } +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -2777,6 +2819,19 @@ static const struct gic_quirk its_quirks[] = { .init = its_enable_quirk_qdf2400_e0065, }, #endif +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + { + /* + * The Socionext Synquacer SoC incorporates ARM's own GIC-500 + * implementation, but with a 'pre-ITS' added that requires + * special handling in software. + */ + .desc = "ITS: Socionext Synquacer pre-ITS", + .iidr = 0x0001143b, + .mask = 0xffffffff, + .init = its_enable_quirk_socionext_synquacer, + }, +#endif { } }; @@ -2806,6 +2861,7 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) inner_domain->parent = its_parent; irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; + inner_domain->flags &= its->msi_domain_flag_mask; info->ops = &its_msi_domain_ops; info->data = its; inner_domain->host_data = info; @@ -2959,6 +3015,7 @@ static int __init its_probe_one(struct resource *res, goto out_free_its; } its->cmd_write = its->cmd_base; + its->fwnode_handle = handle; its_enable_quirks(its);