From patchwork Thu Sep 14 12:57:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112557 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714885qgf; Thu, 14 Sep 2017 06:01:04 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5yh1tCwdkwPDsq/pHmGXbsq7lri/1KibYq2juhYohZFVe3JBBWB5y5HdE2JrYHBX+tpcQP X-Received: by 10.98.196.206 with SMTP id h75mr20789810pfk.35.1505394063828; Thu, 14 Sep 2017 06:01:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394063; cv=none; d=google.com; s=arc-20160816; b=EYrpZ9oL/5CUBvqiUCLCW2E26Xy5E6EKAHC8MPo+RBkJC2nu5za3BiZq5U2XjMdJg4 X1gwWd/tOlg/wRDriWCRWEWvYNZ1rDYusR/r+Z80yswDz9LkTS8hYLXDiidb2XEDf8e3 2RiqbXuO8gV3GtNWkOJRAY16tRnqJnvqScatjuiazyzeRPpECs0ybE44cByJUxF9hMXP KoClXiJBmFWwNDbnuojjk2G5ahMYBHK2hmt36CNees9bSDKzGWvtHAKJG3nSSAWjrNCE sXU/39QdtTLA6R4HU84XT42q4rq3RUBE6DvZ0RVtieeewKheHwgCD/oEdR5JnHwyam7h MJBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=OFLTg5gKWDtX4DwR9iSliarC+D21FTenPPO3Mda24XE=; b=shUBuAjX4dveXv9EZRJaP9igCkRhyDCEWSq+yw8jk+UV7xn/ZUkflQTU7Xv6C1pHpD gfUGL3XAlF5Qm7zqVaWH6igmaYSon64a48+XPyrc+GfTExDTMOl/gDkBb10C3WZbEF0L Fn4k23bWFhLJu83BDVej4yLdc50y4rkMTpRNA72sBarD/+/LW2vEyujAq1L76HRdqYkC Bov+Pi/xNCLdq++fKKc5C2rF+oXkxrWGwIywobG+UXnfRTxZxuXFDo77VTf/bNpTDiw7 VdUnaF/B9t29+RhsEhU47p4JLI9zXR5Gza6zp2+h81fl39UsShULEzqrHY18JvVQaPLl qXWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.01.03; Thu, 14 Sep 2017 06:01:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751335AbdINNBC (ORCPT + 6 others); Thu, 14 Sep 2017 09:01:02 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6481 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751370AbdINNBB (ORCPT ); Thu, 14 Sep 2017 09:01:01 -0400 Received: from 172.30.72.59 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHF34364; Thu, 14 Sep 2017 21:00:59 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:52 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 5/5] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Thu, 14 Sep 2017 13:57:56 +0100 Message-ID: <20170914125756.14836-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> References: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59BA7D8B.010C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a619a19319a561b74f86834c14b34d46 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum [John: add DT support] Signed-off-by: John Garry --- drivers/iommu/arm-smmu-v3.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 568c400..8503f4d 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -608,6 +608,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -674,6 +675,7 @@ struct arm_smmu_option_prop { static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, + { ARM_SMMU_OPT_RESV_HW_MSI, "hisilicon,broken-untranslated-msi" }, { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"}, { 0, NULL}, }; @@ -1934,14 +1936,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2684,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; }