From patchwork Thu Sep 14 12:57:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112556 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714816qgf; Thu, 14 Sep 2017 06:01:01 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6NaPyibOHj9nsf+7WAR+OSWD/dsxQl12ZkT/0gLpLQcM8jNvRFTjF61KOgCjOVXHpuweJ1 X-Received: by 10.98.14.213 with SMTP id 82mr21291584pfo.320.1505394061211; Thu, 14 Sep 2017 06:01:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394061; cv=none; d=google.com; s=arc-20160816; b=ugFC+9LZybf6MXuWuiy86WD90DObOtq5jzESyfhrF8ZZ0Vsqj9WD7afvyevzPe/Q5U Ow+OsXtiJ+L+lj1oonEJuOfJD4NejTmKzd0Qj+ztyb/McEAlX8o0WqC/EWaXuuGZuVzk CrGMTuUgpQLqJIxxMDwa+pBID7cd3Ey8O7cW5B+OdcfUdc1BEDldv6iG2HrbtrZILrmh bvczi987Pbgum/SU3rsx1XwewKrFRfpiRhUH6keVF4zFiPzzhLAHk4GltVd7jpE97a8L auaF/JfpEpR9TEkKQ4mYhmyPLXxuEEUqv3NbcMJ1yMXGAcYJ+83gWL2UWc9l8TsCNyoo dRpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=MHdCOhdk71Roxd/yglkBE1k5F56IYPucJbseVzdpbmM=; b=NMiMtUrLtpVjmeAbcCrK1l40d0wIr79xGbU7S0d3WhmyFvCIuR7WUf0aTvRY5vfGDQ TAYAudx7ys3Fo8jDAsiyQ0zbEObaE1qNaziwjnbwuC1OeMvhrqRcqzMAXr4Pznj5FPQq xiByPmyTKrzdMxjROaoCFxt9zN48+nsWO84hJsIrrNjh+PBGv2cR253RubO/VVJW2fRO IAch7O8O9YoWKqxgzHyEU58STG0JwjM4J7NvE0JPpZzKYSyMfHfAka+1o4et/2VeV0ZR Ta5TB25K27IWghegvK94Mqo5QygyF3OH8jfxU1SvFTgUadqMCSSpgYldNwgxwtH80L8h qj4Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.00.59; Thu, 14 Sep 2017 06:01:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751365AbdINNA5 (ORCPT + 6 others); Thu, 14 Sep 2017 09:00:57 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6480 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751335AbdINNA4 (ORCPT ); Thu, 14 Sep 2017 09:00:56 -0400 Received: from 172.30.72.59 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHF34348; Thu, 14 Sep 2017 21:00:54 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:43 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 3/5] iommu/of: Add msi address regions reservation helper Date: Thu, 14 Sep 2017 13:57:54 +0100 Message-ID: <20170914125756.14836-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> References: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59BA7D86.0122, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8efd3143354b48dbe223742ebc3bebbe Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: John Garry On some platforms msi-controller address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves msi address regions through device tree msi mapping, so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. Signed-off-by: John Garry Signed-off-by: Shameer Kolothum --- drivers/iommu/of_iommu.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/of_iommu.h | 10 ++++ 2 files changed, 127 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 8cb6082..f2d1a76 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -246,6 +247,122 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, return ops; } +/** + * of_iommu_msi_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of reserved regions on success (0 if no associated + * msi parent), appropriate error value otherwise. + */ +int of_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + struct device_node *np; + struct resource res; + int i, resv = 0, mappings = 0; + + if (dev_is_pci(dev)) { + struct device *dma_dev, *bridge; + struct of_phandle_args iommu_spec; + struct pci_dev *pdev = to_pci_dev(dev); + int err, count; + u32 rid, map_mask; + const __be32 *msi_map; + + bridge = pci_get_host_bridge_device(pdev); + dma_dev = bridge->parent; + pci_put_host_bridge_device(bridge); + + if (!dma_dev->of_node) + return -ENODEV; + + iommu_spec.args_count = 1; + np = iommu_spec.np = dma_dev->of_node; + pci_for_each_dma_alias(pdev, __get_pci_rid, &iommu_spec); + + rid = iommu_spec.args[0]; + if (!of_property_read_u32(np, "msi-map-mask", &map_mask)) + rid &= map_mask; + + msi_map = of_get_property(np, "msi-map", NULL); + if (!msi_map) + return -ENODEV; + + mappings = of_count_phandle_with_args(np, "msi-map", NULL) / 4; + + for (i = 0, count = mappings; i < count; i++, msi_map += 4) { + struct device_node *msi_node; + u32 rid_base, rid_len, phandle; + + rid_base = be32_to_cpup(msi_map + 0); + phandle = be32_to_cpup(msi_map + 1); + rid_len = be32_to_cpup(msi_map + 3); + + /* check rid is within range */ + if (rid < rid_base || rid >= rid_base + rid_len) { + mappings--; + continue; + } + + msi_node = of_find_node_by_phandle(phandle); + if (!msi_node) + return -ENODEV; + + err = of_address_to_resource(msi_node, 0, &res); + of_node_put(msi_node); + if (err) + return err; + + region = iommu_alloc_resv_region(res.start, + resource_size(&res), + prot, IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } else if (dev->of_node) { + struct device_node *msi_np; + int index = 0; + int tuples; + + np = dev->of_node; + + tuples = of_count_phandle_with_args(np, "msi-parent", NULL); + + while (index < tuples) { + int msi_cells = 0; + int err; + + msi_np = of_parse_phandle(np, "msi-parent", index); + if (!msi_np) + return -ENODEV; + + of_property_read_u32(msi_np, "#msi-cells", &msi_cells); + + err = of_address_to_resource(msi_np, 0, &res); + of_node_put(msi_np); + if (err) + return err; + + mappings++; + + region = iommu_alloc_resv_region(res.start, + resource_size(&res), + prot, IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + index += 1 + msi_cells; + } + } + + return (resv == mappings) ? resv : -ENODEV; +} + static int __init of_iommu_init(void) { struct device_node *np; diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h index 13394ac..9267772 100644 --- a/include/linux/of_iommu.h +++ b/include/linux/of_iommu.h @@ -14,6 +14,9 @@ extern int of_get_dma_window(struct device_node *dn, const char *prefix, extern const struct iommu_ops *of_iommu_configure(struct device *dev, struct device_node *master_np); +extern int of_iommu_msi_get_resv_regions(struct device *dev, + struct list_head *head); + #else static inline int of_get_dma_window(struct device_node *dn, const char *prefix, @@ -29,6 +32,13 @@ static inline const struct iommu_ops *of_iommu_configure(struct device *dev, return NULL; } +static int of_iommu_msi_get_resv_regions(struct device *dev, + struct list_head *head) +{ + return -ENODEV; +} + + #endif /* CONFIG_OF_IOMMU */ extern struct of_device_id __iommu_of_table;