From patchwork Mon Aug 28 18:04:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 111176 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp131739qge; Mon, 28 Aug 2017 11:04:51 -0700 (PDT) X-Received: by 10.99.119.203 with SMTP id s194mr1375335pgc.38.1503943491006; Mon, 28 Aug 2017 11:04:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503943490; cv=none; d=google.com; s=arc-20160816; b=eTr7I0HcwJVbJJVvw2g1hWEUXALZkVj4wzB/VcxN9xGx8MIcd1JRqBUIT6Na3TcmBx UOIjwZ68pNA+PzyWaT2H1+ub1oDqa9aqVqKULSWk3Xn9obIiWCv8CGRK4PAAGfTcOW2s O6iCVZzGZWHGQtNOLWqTRY69FJH7ZpXA1d7qdK83uSiHrKc/5IVaztWYO0F3L2BEPnOY UIeyhodx2btYySWeBXhN1dvxi76MmJNFs3NlOANM8e3Qd6nZtJ0xdryjXnFreEiYlyGu 1LfyNHl0v9AVXFFDMvG5RfbukfpLMml7rF/BM/5Infggtk372QHbuADeHnAmZBTPXV+f 9YOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=m5herz+06aaJVMXg4lIfL34Rku4sBwMis8i8aio+8MQ=; b=ZMo5KimKYu+l6j95/Dan2WMxweY29cc1awCLYdI67DAxiA26N3c5+Sj53YVBwyFJDA SFFgIsOzglmu/2h4rB/xU4QZCmF43MKN2cSSzDtj43VxPGCaid0+J2Gma7U6LmjHc3zl BBhQ5PveoV9VmBtrO+EQYwo16sBydhYejazwExdYvWzVgO47WHYYCqaOIBwD6fQbocyo y9+OTu2cts4zKRvDv8kWUH2jnZfwMvyAmCeRz21GNmLFS1jK1N5akCpZzO3oD1lV4Z8G AjR7UlcFW+23LlJLEvHlEfxoyXaHgOSb5vpW4MDeQISkBXkzWV4lfu07ZBWbah/RxxRa vqGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ci5B12lV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b8si722356ple.299.2017.08.28.11.04.50; Mon, 28 Aug 2017 11:04:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ci5B12lV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751203AbdH1SEt (ORCPT + 6 others); Mon, 28 Aug 2017 14:04:49 -0400 Received: from mail-wr0-f170.google.com ([209.85.128.170]:33652 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751161AbdH1SEt (ORCPT ); Mon, 28 Aug 2017 14:04:49 -0400 Received: by mail-wr0-f170.google.com with SMTP id k94so3852819wrc.0 for ; Mon, 28 Aug 2017 11:04:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3wTCZGKm5urtjkZ+N6IJvAGmtQOruHhgXRZsj+N+174=; b=ci5B12lVF9vjM/da7zdIqQHdxQWJAnVPtStVnclPUbGjTt54RMW8gzCUFF9f/AbOnP zDf1McCVS1QmE4brKOponnOqYxyp7Rw5018Bp+8er2y5vzdcENvObDWpXTFkbNfyxyPY Qm3Jt2RSIomNa1LwQiRsrO+NB8x4h7/2aHrNY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3wTCZGKm5urtjkZ+N6IJvAGmtQOruHhgXRZsj+N+174=; b=Y6dbgp9q28/gF/EoTs0qHC5hgg2hFzr+VuGcUkSA+JdWhcT8zjrmQCB0/8QK648BeZ lHfXu6Ts9WWgtIYroU2n9WKi+O8Lt5WgXb3c4pTfRsKkqIRLp9fTYR9FLeenlMapqfbz AHJYU6ibiUCvD6pyJTMqRvtYnsDuC9vM+n24NLp0yjj/9TwtA+zTJp0Hy7zNRhyV8Ucr 48IhU8l2eDAhNNhle/hjMT225sJeXfcPjal5JeFUlKP0yvqQsftB+eN30X0s86hYtdEI qQlnIuElx/0GVEaHNdnFOO4S/SxF8o00JGi6SYwnC2HQeZcH+1OuKmucEYUkPsTKo7+9 2aZw== X-Gm-Message-State: AHYfb5hNv/0tlEj67V1ERO20RfF+chhTJWPRfCvhR50iMRRD1I8kg5cW VHsjHqicohfZT9oc X-Received: by 10.223.174.89 with SMTP id u25mr1036918wrd.246.1503943487518; Mon, 28 Aug 2017 11:04:47 -0700 (PDT) Received: from localhost.localdomain ([105.133.189.215]) by smtp.gmail.com with ESMTPSA id i22sm1335922wrf.18.2017.08.28.11.04.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 11:04:46 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, mw@semihalf.com, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Jingoo Han , Joao Pinto , Rob Herring Subject: [PATCH v3 1/2] pci: designware: add driver for DWC controller in ECAM shift mode Date: Mon, 28 Aug 2017 19:04:36 +0100 Message-Id: <20170828180437.2646-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170828180437.2646-1-ard.biesheuvel@linaro.org> References: <20170828180437.2646-1-ard.biesheuvel@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some implementations of the Synopsys Designware PCIe controller implement a so-called ECAM shift mode, which allows a static memory window to be configured that covers the configuration space of the entire bus range. If the firmware performs all the low level configuration that is required to expose this controller in a fully ECAM compatible manner, we can simply describe it as "pci-host-ecam-generic" and be done with it. However, it appears that in some cases (one of which is the Armada 80x0), the IP is synthesized with an ATU window size that does not allow the first bus to be mapped in a way that prevents the device on the downstream port from appearing more than once. So implement a driver that relies on the firmware to perform all low level initialization, and drives the controller in ECAM mode, but overrides the config space accessors to take the above quirk into account. Note that, unlike most drivers for this IP, this driver does not expose a fake bridge device at B/D/F 00:00.0. There is no point in doing so, given that this is not a true bridge, and does not require any windows to be configured in order for the downstream device to operate correctly. Omitting it also prevents the PCI resource allocation routines from handing out BAR space to it unnecessarily. Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Joao Pinto Signed-off-by: Ard Biesheuvel --- drivers/pci/dwc/Kconfig | 11 +++ drivers/pci/dwc/Makefile | 1 + drivers/pci/dwc/pcie-designware-ecam.c | 77 ++++++++++++++++++++ 3 files changed, 89 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index d275aadc47ee..477576d07911 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -169,4 +169,15 @@ config PCIE_KIRIN Say Y here if you want PCIe controller support on HiSilicon Kirin series SoCs. +config PCIE_DW_HOST_ECAM + bool "Synopsys DesignWare PCIe controller in ECAM mode" + depends on OF && PCI + select PCI_HOST_COMMON + select IRQ_DOMAIN + help + Add support for Synopsys DesignWare PCIe controllers configured + by the firmware into ECAM shift mode. In some cases, these are + fully ECAM compliant, in which case the pci-host-generic driver + may be used instead. + endmenu diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile index c61be9738cce..7d5a23e5b767 100644 --- a/drivers/pci/dwc/Makefile +++ b/drivers/pci/dwc/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o +obj-$(CONFIG_PCIE_DW_HOST_ECAM) += pcie-designware-ecam.o obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),) diff --git a/drivers/pci/dwc/pcie-designware-ecam.c b/drivers/pci/dwc/pcie-designware-ecam.c new file mode 100644 index 000000000000..ede627d7d08b --- /dev/null +++ b/drivers/pci/dwc/pcie-designware-ecam.c @@ -0,0 +1,77 @@ +/* + * Driver for mostly ECAM compatible Synopsys dw PCIe controllers + * configured by the firmware into RC mode + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (C) 2014 ARM Limited + * Copyright (C) 2017 Linaro Limited + * + * Authors: Will Deacon + * Ard Biesheuvel + */ + +#include +#include +#include +#include +#include +#include + +static int pci_dw_ecam_config_read(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pci_config_window *cfg = bus->sysdata; + + /* + * The Synopsys dw PCIe controller in RC mode will not filter type 0 + * config TLPs sent to devices 1 and up on its downstream port, + * resulting in devices appearing multiple times on bus 0 unless we + * filter them here. + */ + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + return pci_generic_config_read(bus, devfn, where, size, val); +} + +static int pci_dw_ecam_config_write(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) +{ + struct pci_config_window *cfg = bus->sysdata; + + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return pci_generic_config_write(bus, devfn, where, size, val); +} + +static struct pci_ecam_ops pci_dw_ecam_bus_ops = { + .pci_ops.map_bus = pci_ecam_map_bus, + .pci_ops.read = pci_dw_ecam_config_read, + .pci_ops.write = pci_dw_ecam_config_write, + .bus_shift = 20, +}; + +static const struct of_device_id pci_dw_ecam_of_match[] = { + { .compatible = "marvell,armada8k-pcie-ecam" }, + { .compatible = "socionext,synquacer-pcie-ecam" }, + { .compatible = "snps,dw-pcie-ecam" }, + { }, +}; + +static int pci_dw_ecam_probe(struct platform_device *pdev) +{ + return pci_host_common_probe(pdev, &pci_dw_ecam_bus_ops); +} + +static struct platform_driver pci_dw_ecam_driver = { + .driver.name = "pcie-designware-ecam", + .driver.of_match_table = pci_dw_ecam_of_match, + .driver.suppress_bind_attrs = true, + .probe = pci_dw_ecam_probe, +}; +builtin_platform_driver(pci_dw_ecam_driver);