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[209.132.180.67]) by mx.google.com with ESMTP id n34si1305188pld.268.2017.06.14.20.07.01; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.b=HNvNwvSK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752352AbdFODG6 (ORCPT + 7 others); Wed, 14 Jun 2017 23:06:58 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:34248 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752140AbdFODG4 (ORCPT ); Wed, 14 Jun 2017 23:06:56 -0400 Received: by mail-pf0-f182.google.com with SMTP id s66so1410201pfs.1 for ; Wed, 14 Jun 2017 20:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l8HEG60ACS51qmx+5dpnRvo8Cd2RySFdr2XUItZtdDs=; b=HNvNwvSKYLHcfREvSLsqfOue4Xem235gEccuytGbg8MaIdOBXmx4n8WpaE5oUnPz0Z YqGU6H5TFzcGksR6jbZIP+R+QSmfQKDxhYHhhh9QEWsUIpu7rlQm3wGz2hCyQU7ukasM yMMZKiq/Y9hxcq0PmI+4G6YwufIIBIzWJ0LCo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l8HEG60ACS51qmx+5dpnRvo8Cd2RySFdr2XUItZtdDs=; b=rW3yhRrqtFSsGjsJKHO9ApAaXlGognFBLK6oC9vBbcLsqz70lyv69ThGE8a3CX2H6X lJWo0cBfcOaglE7vwrKTwKT2hZzbCYRCeXFSDeuJDZlEAEQeY+5wjEaHcpPEBLyfw8yF asg/s1Z5UiJI55cqzXmluEyV4VGj60oolkQJ0bDDNB89IkmRNkkQ6VU+NkeoqYnQ0Rw9 Hxw7h9j6S7LGTE8UE512NVMSd4Anjge3WWge3Qvg2zxa3yIW6GBM+x7gpzZYtOtZdMwC I2/VJcT/BeTFj/apVRjoUQjfvkcW5CUfGtlXhysgLq0BcHNPDTeqpDUUbwOLBo9RoMFq DnTQ== X-Gm-Message-State: AKS2vOwfRvE6nUVVxVQ7+h2Bltc8HZz/mxnbgcaXjp1qw7g1oXBCivkz XfpmYEZs/2cQuN3Y X-Received: by 10.84.142.131 with SMTP id 3mr2465505plx.211.1497496015763; Wed, 14 Jun 2017 20:06:55 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.06.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:06:55 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Xiaowei Song Subject: [PATCH v4 14/20] dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs Date: Thu, 15 Jun 2017 11:04:11 +0800 Message-Id: <20170615030417.14059-15-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Xiaowei Song This patch adds document for PCIe of Kirin SoC series. Signed-off-by: Xiaowei Song Acked-by: Rob Herring --- .../devicetree/bindings/pci/kirin-pcie.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt new file mode 100644 index 0000000..68ffa0f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -0,0 +1,50 @@ +HiSilicon Kirin SoCs PCIe host DT description + +Kirin PCIe host controller is based on Designware PCI core. +It shares common functions with PCIe Designware core driver +and inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties +- compatible: + "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC +- reg: Should contain rc_dbi, apb, phy, config registers location and length. +- reg-names: Must include the following entries: + "dbi": controller configuration registers; + "apb": apb Ctrl register defined by Kirin; + "phy": apb PHY register defined by Kirin; + "config": PCIe configuration space registers. +- reset-gpios: The gpio to generate PCIe perst assert and deassert signal. + +Optional properties: + +Example based on kirin960: + + pcie@f4000000 { + compatible = "hisilicon,kirin-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + };