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[209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.08; Wed, 07 Jun 2017 14:28:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751506AbdFGV2G (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:06 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:62917 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751299AbdFGV2A (ORCPT ); Wed, 7 Jun 2017 17:28:00 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRXtK029829; Wed, 7 Jun 2017 16:27:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870853; bh=XskRseTFiiumbEDOCRVE9DhX/AJS8JoW7FNcwV+XO2g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Fyvxj2OFWdm/I0mrVqMIRpdCBpcqr0iE0GbUNsat6oZnp/e6q6xVPEv1HeVJ1qOBX Zo44B+DYSKTO/d2+S7GOldUQcXOQ34GTkb/6qENJWsVIZkfclyvEcI5Bxr7Rv9heTk Rukew4vGdXBiY0zLg+pWWi+/cdlfbRMxKwjhuE/4= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXOa003998; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWBL015971; Wed, 7 Jun 2017 16:27:33 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRW307114; Wed, 7 Jun 2017 16:27:32 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:28 -0500 Message-ID: <20170607212730.33002-5-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfaf27215901..8a82490035d9 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -338,6 +338,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { @@ -349,6 +351,8 @@ reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -659,6 +663,8 @@ reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck {