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[209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.21.37; Thu, 25 May 2017 01:21:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423678AbdEYIVL (ORCPT + 7 others); Thu, 25 May 2017 04:21:11 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:35719 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423683AbdEYIUN (ORCPT ); Thu, 25 May 2017 04:20:13 -0400 Received: by mail-pf0-f181.google.com with SMTP id n23so160522487pfb.2 for ; Thu, 25 May 2017 01:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=dCcyZBuyrZSkKVNLffeQP85uXVKvTvvJ85ai+4Edg9zN4qdsdGwVzStU4i4X6cP1By ui1ZNDOcLgFhpIwahgv931Y06c2XjaFCfzJA3ygXc+oq5Bj9ZZ0AgpaiiR2Vj7H606Z8 QiJAFNkaR9syuqySJVvMgZDD1i5Siv3RLJaY0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=lUwOaXd1zt9oO8HbDlFHPoKhpw64Ll11QgMerH24khBtMq3eRYz8HZ4Xws7pjUb35d l91FbxrWGbqDXxuD3Y1Li5Ex3JF1H8XLSqUsbQ623jxoZA0n30zLZJfYqzsmcyHzBYP1 2mSlYArq0dhWFM4ssB1znEVaXSDf/Ha45KS/IiBI+tdN18WP2nxjcawIUILRmvr6pxXc yzUYz/VjhiPrNbmYI5x/Jj286J5CfYV6cFoxOHnZq/bxI5CTMkwYSuxbcALLQRNX0+9V pC767KOTMGAo4aYtY3ZW2htGl7yEHx9Zwylo2RywDwA1YtA3mfvQ4bSltlTtCP940OrU er4w== X-Gm-Message-State: AODbwcBRG8UtGUBYH8NHf+6q0yKi7OHOMqm3BM2VjJk2Ezb7mjufYuqc pY43yQuwELvN54pnjgTJBw== X-Received: by 10.99.126.92 with SMTP id o28mr45207549pgn.63.1495700407718; Thu, 25 May 2017 01:20:07 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.20.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:20:07 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin , Guodong Xu Subject: [PATCH v2 12/12] arm64: dts: hi3660: add spi device nodes Date: Thu, 25 May 2017 16:18:54 +0800 Message-Id: <20170525081854.4701-13-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Wang Xiaoyin Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960. On HiKey960: - SPI2 is wired out through low speed expansion connector. - SPI3 is wired out through high speed expansion connector. Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 12 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 30 +++++++++++++++++++++++ 2 files changed, 42 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 9ecf6c6..ca448f0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -142,3 +142,15 @@ label = "LS-UART1"; status = "okay"; }; + +&spi2 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&spi3 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3b2a3a7..a6b91f1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -713,5 +713,35 @@ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; clock-names = "apb_pclk"; }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; }; };