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[209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.20.48; Thu, 25 May 2017 01:20:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423685AbdEYIUZ (ORCPT + 7 others); Thu, 25 May 2017 04:20:25 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:34739 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423670AbdEYITx (ORCPT ); Thu, 25 May 2017 04:19:53 -0400 Received: by mail-pf0-f173.google.com with SMTP id 9so160433422pfj.1 for ; Thu, 25 May 2017 01:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4jQ3O/BMN/V4rkRyXEsB59sUYtfxxLmhwukoxiNK9cI=; b=c8LMCRLM8YbsxoncV7Xv8/2/t5fJtTmuRSqqusnTvlVGnOnPeeiFdOk1pHmcnd0VOR SSblEn14DoYbdAFZjxbHl6/HLfHoef6lZnl4qhSbJy15NAC0pPa5oZ1o9PZ6WfLkZqSB f/zWtLh3baYzZ4YcLyzoomj1q/sGzVe6drj/c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4jQ3O/BMN/V4rkRyXEsB59sUYtfxxLmhwukoxiNK9cI=; b=mlAsqSH6PArq+/UQbImDSsCQ9UoHso6uPHGDDB1X1rW9rCZ3QaPAYMXYyCT3A+Ma8m 7JWMLuNFRRnCKy6+FV/1wHKuqyO1KOBXeQQeTMVxLrsNvkhSWCNzlLUxRpAhugi913sZ g8hkMNqte/16OLqlWs13xkgl19gqE2LGkLFxeTO9mRpN23p8HdXk3gb3PdfknDUv/lQ5 8T7By9KkREgMbFndQnw+Kt0Oib4J45aXkH+ZNA0rs0OuGuxht5ucXoyCitH7dubzuYdk CQv9s4poUSQjzdRBH+QhP49wR5tkJW0hrEJk/339Le1nVWkhPDhSgyQj2IRnQn5Ci+Jw V4DA== X-Gm-Message-State: AODbwcAL3PRsNcMppQA5Zr5c4bZ5Y/gfM8dw67XJT3S21JKn4N+5OX40 WA01amljOlWm/N0I X-Received: by 10.98.151.2 with SMTP id n2mr43679053pfe.29.1495700392646; Thu, 25 May 2017 01:19:52 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:52 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 09/12] arm64: dts: hi3660: Add pl031 rtc node Date: Thu, 25 May 2017 16:18:51 +0800 Message-Id: <20170525081854.4701-10-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chen Feng Add dts node to enable pl031 rtc. Signed-off-by: Chen Feng Acked-by: Rob Herring --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 7a90c92..3b2a3a7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -326,6 +326,14 @@ status = "disabled"; }; + rtc0: rtc@fff04000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0Xfff04000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + }; + gpio0: gpio@e8a0b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0b000 0 0x1000>;