From patchwork Tue May 23 09:48:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 100364 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp234620qge; Tue, 23 May 2017 02:49:20 -0700 (PDT) X-Received: by 10.84.134.34 with SMTP id 31mr34225455plg.178.1495532960025; Tue, 23 May 2017 02:49:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495532960; cv=none; d=google.com; s=arc-20160816; b=Gz8F1L0BuagkHPkwe9XQ3dbWjAIMvb0tHstlwVK3SxgELs415ZYTkfs0H2Ih98esZW hP+li2PLTiPQqzBrZM/MLvkGS9GuZmJ9PqY13KwY60awtJTGW29TKrHEPPkjFy9sUEAm gSWaDt+LLU8bq3HrvkaXflDONkM9JPjLyCXH4OBh0ydWWRj6WTeHf982SC71YQoRlUoA hSCe+Y4/5iKjkU5tmxIlu9NS/KPxpMOytvL7fpMYWmWCOx23k7BeudjMXGWF8v+oN7Jf PQgOYQBBYlx+hDH6ONQzI814LzPvyfAZDUm+tClSrLgbRIyrM0PcyAP4QCf7m52BknI8 gl0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=XTGDh0Htr23GACME+4cbNfFEX7kynCq9ATFxuT3m25s=; b=DXyxzt695vC5Lpc7cN5dRaCPoWmwhbwSz5AN+iK7YYpeBukBH2o9dVNRHtORn+tLOh elgafLWVXpO/fe0sOJTApk+CdFdjjv4M41Awt0neB94ODFnL+6bTOVNju6a+QF9n3yUK MPaccwXvRXtU1jC15vpSZPDkyEh+3ieIcdxthdWaWU5WhfUIP3ha9StB53thGYRRua41 dPxZ5LwtncgAh+7VXixsN3Y0upYIzwqzo2vniN8/EvOCX2pNbD/lCC1F/cjkinUKIgph br0uWw0kdtqbc9AZFyCT+V6+xPEZBHx6g3+4Vxm73YF1gLVjNHHLgwaW4tpijK6TwlXi 6hqw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u18si2222730plj.150.2017.05.23.02.49.19; Tue, 23 May 2017 02:49:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965563AbdEWJtK (ORCPT + 7 others); Tue, 23 May 2017 05:49:10 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:36417 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965572AbdEWJtG (ORCPT ); Tue, 23 May 2017 05:49:06 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id E0C82207FD; Tue, 23 May 2017 11:49:03 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id B7A842055D; Tue, 23 May 2017 11:48:27 +0200 (CEST) From: Quentin Schulz To: fugang.duan@nxp.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: Quentin Schulz , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@free-electrons.com Subject: [PATCH v2] net: fec: add post PHY reset delay DT property Date: Tue, 23 May 2017 11:48:08 +0200 Message-Id: <20170523094808.11102-1-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some PHY require to wait for a bit after the reset GPIO has been toggled. This adds support for the DT property `phy-reset-post-delay` which gives the delay in milliseconds to wait after reset. If the DT property is not given, no delay is observed. Post reset delay greater than 1000ms are invalid. Signed-off-by: Quentin Schulz --- v2: - return -EINVAL when phy-reset-post-delay is greater than 1000ms instead of defaulting to 1ms, - remove `default to 1ms` when phy-reset-post-delay > 1000Ms from DT binding doc and commit log, - move phy-reset-post-delay property reading before devm_gpio_request_one(), Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++ drivers/net/ethernet/freescale/fec_main.c | 16 +++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Fugang Duan diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index a1e3693cca16..6f55bdd52f8a 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -15,6 +15,10 @@ Optional properties: - phy-reset-active-high : If present then the reset sequence using the GPIO specified in the "phy-reset-gpios" property is reversed (H=reset state, L=operation state). +- phy-reset-post-delay : Post reset delay in milliseconds. If present then + a delay of phy-reset-post-delay milliseconds will be observed after the + phy-reset-gpios has been toggled. Can be omitted thus no delay is + observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. - phy-supply : regulator that powers the Ethernet PHY. - phy-handle : phandle to the PHY device connected to this device. - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 56a563f90b0b..f7c8649fd28f 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -3192,7 +3192,7 @@ static int fec_reset_phy(struct platform_device *pdev) { int err, phy_reset; bool active_high = false; - int msec = 1; + int msec = 1, phy_post_delay = 0; struct device_node *np = pdev->dev.of_node; if (!np) @@ -3209,6 +3209,11 @@ static int fec_reset_phy(struct platform_device *pdev) else if (!gpio_is_valid(phy_reset)) return 0; + err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); + /* valid reset duration should be less than 1s */ + if (!err && phy_post_delay > 1000) + return -EINVAL; + active_high = of_property_read_bool(np, "phy-reset-active-high"); err = devm_gpio_request_one(&pdev->dev, phy_reset, @@ -3226,6 +3231,15 @@ static int fec_reset_phy(struct platform_device *pdev) gpio_set_value_cansleep(phy_reset, !active_high); + if (!phy_post_delay) + return 0; + + if (phy_post_delay > 20) + msleep(phy_post_delay); + else + usleep_range(phy_post_delay * 1000, + phy_post_delay * 1000 + 1000); + return 0; } #else /* CONFIG_OF */