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[209.132.180.67]) by mx.google.com with ESMTP id s5si14911403plj.274.2017.04.03.10.58.48; Mon, 03 Apr 2017 10:58:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752630AbdDCR6s (ORCPT + 7 others); Mon, 3 Apr 2017 13:58:48 -0400 Received: from mail-oi0-f49.google.com ([209.85.218.49]:34310 "EHLO mail-oi0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752602AbdDCR6r (ORCPT ); Mon, 3 Apr 2017 13:58:47 -0400 Received: by mail-oi0-f49.google.com with SMTP id d2so2391559oig.1 for ; Mon, 03 Apr 2017 10:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=hl7TEEhstLqk7BYZ5BkASqB9ouYSj9lwoZzpJ99TdwM=; b=YGJTIO97IXlxgdZUWFOksuhCQw3/2OF5K2kGNRntpjQGApby2h8LQmb6oJ6BrEjxb5 NaXdnIB/3wlE/bnbznbvWyH/yLIFjDj9lGjLe0aCrvygSw4Wv0zs9j17tD7z8tF/hWlc 8CSCiUOHNi89Xyl1G2+sPXnLP1mh3vQx5DqHI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=hl7TEEhstLqk7BYZ5BkASqB9ouYSj9lwoZzpJ99TdwM=; b=SD6Vx+7LVRtNBuTpLZrHjLAa0wad779YmXd1UlhKtVOw+Xd68+hKBk67/crSyoqzOH EPngkhbWbuMqkuMnhhK3PuPXOGMbTpiufnrDAcA4QP5MDSjSY2IPgxMlmh3lH3fqKpui 0TfAQgBp27fFsL1s6/mj71k5QzKCAlCk8WccGwldtsCFH0jhSamN40ulZxUybKCvbH39 DQ9VWMIXqnw3d8RwLI8IXaF31V1rS1yhoYWywS19rl9UUnNJj18FnLIZp3E01/C0YnCe X03jUAI4cz3+33Uvx3CXyTg49LZ7cRJIR31ywFMVy2g0z+X9nS7pnp8oSOR+yfVpC8e+ 62gw== X-Gm-Message-State: AFeK/H32YVs2ykH4ZQWlhu41M/fSGtPILXtQvL1mLHTjTs7qxz3pt5iKlyE8il0cX0mD4cA8 X-Received: by 10.157.9.244 with SMTP id 49mr10851028otz.194.1491242326770; Mon, 03 Apr 2017 10:58:46 -0700 (PDT) Received: from localhost.localdomain ([2602:306:839b:d67e:e073:9aec:8b08:2b8e]) by smtp.gmail.com with ESMTPSA id m11sm5751955oif.17.2017.04.03.10.58.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Apr 2017 10:58:46 -0700 (PDT) From: Kumar Gala To: Rob Herring Cc: Kumar Gala , Device Tree Mailing List , Mark Rutland Subject: [PATCH v2] dt-bindings: arm, nvic: Binding for ARM NVIC interrupt controller on Cortex-M Date: Mon, 3 Apr 2017 12:58:42 -0500 Message-Id: <20170403175842.17289-1-kumar.gala@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Kumar Gala --- * Dropped arm,nvic, fixed up example to match .../bindings/interrupt-controller/arm,nvic.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt new file mode 100644 index 0000000..386ab37 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt @@ -0,0 +1,36 @@ +* ARM Nested Vector Interrupt Controller (NVIC) + +The NVIC provides an interrupt controller that is tightly coupled to +Cortex-M based processor cores. The NVIC implemented on different SoCs +vary in the number of interrupts and priority bits per interrupt. + +Main node required properties: + +- compatible : should be one of: + "arm,v6m-nvic" + "arm,v7m-nvic" + "arm,v8m-nvic" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 2. + + The 1st cell contains the interrupt number for the interrupt type. + + The 2nd cell is the priority of the interrupt. + +- reg : Specifies base physical address(s) and size of the NVIC registers. + This is at a fixed address (0xe000e100) and size (0xc00). + +- arm,num-irq-priority-bits: The number of priority bits implemented by the + given SoC + +Example: + + intc: interrupt-controller@e000e100 { + compatible = "arm,v7m-nvic"; + #interrupt-cells = <2>; + #address-cells = <1>; + interrupt-controller; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <4>; + };