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[209.132.180.67]) by mx.google.com with ESMTP id v2si428945itd.11.2017.03.27.11.10.50; Mon, 27 Mar 2017 11:10:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751564AbdC0SKQ (ORCPT + 7 others); Mon, 27 Mar 2017 14:10:16 -0400 Received: from mail-ot0-f169.google.com ([74.125.82.169]:35118 "EHLO mail-ot0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751533AbdC0SKO (ORCPT ); Mon, 27 Mar 2017 14:10:14 -0400 Received: by mail-ot0-f169.google.com with SMTP id y88so36268045ota.2 for ; Mon, 27 Mar 2017 11:09:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=r69Z5LlQ03nprY5XKODrsdmMoLQjc1mkMFVNtlAkA0A=; b=AJiMbg3a32IHJNdnkb5rPjsGmoeSl1LBBKv133vHQ2ldZYiXyYYA9vuDpck97Q7jIR bYPd5XLm8c4Q/a2jhusdj5tm8s3WfDSkPl/EPoI3VJiLI9KI3lXpcfLVWcY/aihn0K98 RgsY0F5KSHYWCV63pOUj/BCmuh84ITqlfsAos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=r69Z5LlQ03nprY5XKODrsdmMoLQjc1mkMFVNtlAkA0A=; b=uJ54uhCLz6GEL+hUIjd1l3O2ozi6h+E2z1uKSMZk493su6SsS5myWr6Z3wtwze7dmh PfjCvWiV6RY5LFF6KeNA7kV6h+HIpIcBp1POU/iv7ZLQGbAa65E7T6wV7Ow1nQG5T/33 kqx33Apop1ATGUH1PlELoZRhwnS3GqtviIqhmJYCUtUHd8J0SImOE7umGXLd+k/cdPfx KRfHfwsPjU0n+ipo4r2ISXSXrkgYBL7Vg4WI3BggPxZJdh66rZX1X6e2RBjVPHXMIvHS y3Rdvu/kwvn8hTU+mOPsAuM3R8k9wepiul3+v0iMmhvd92K41OtiGqCO+DaLAajcRoFH Z3dA== X-Gm-Message-State: AFeK/H2SqHSFiSkiZeH+HEQobkhiYJYauIDICLgaxQdkSSl0u5Rsy+0B7khZQX+3ql89LUwe X-Received: by 10.157.51.61 with SMTP id f58mr12945177otc.18.1490638150153; Mon, 27 Mar 2017 11:09:10 -0700 (PDT) Received: from localhost.localdomain ([2602:306:839b:d67e:e073:9aec:8b08:2b8e]) by smtp.gmail.com with ESMTPSA id c62sm510899otb.48.2017.03.27.11.09.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Mar 2017 11:09:09 -0700 (PDT) From: Kumar Gala To: robh+dt@kernel.org Cc: Kumar Gala , mark.rutland@arm.com, devicetree@vger.kernel.org Subject: [PATCH] dt-bindings: arm, nvic: Binding for ARM NVIC interrupt controller on Cortex-M Date: Mon, 27 Mar 2017 13:09:05 -0500 Message-Id: <20170327180905.32498-1-kumar.gala@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Kumar Gala --- Note: This is a new binding and not used by the linux kernel code right now for the nvic. The intent would be to support both the current 'arm,armv7m-nvic' compatible and this binding in the code in the future. The 'arm,armv7m-nvic' doesnt have any binding spec covering it today. .../bindings/interrupt-controller/arm,nvic.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt new file mode 100644 index 0000000..60ee89c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt @@ -0,0 +1,37 @@ +* ARM Nested Vector Interrupt Controller (NVIC) + +The NVIC provides an interrupt controller that is tightly coupled to +Cortex-M based processor cores. The NVIC implemented on different SoCs +vary in the number of interrupts and priority bits per interrupt. + +Main node required properties: + +- compatible : should be one of: + "arm,v6m-nvic" + "arm,v7m-nvic" + "arm,v8m-nvic" + "arm,nvic" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 2. + + The 1st cell contains the interrupt number for the interrupt type. + + The 2nd cell is the priority of the interrupt. + +- reg : Specifies base physical address(s) and size of the NVIC registers. + This is at a fixed address (0xe000e100) and size (0xc00). + +- arm,num-irq-priority-bits: The number of priority bits implemented by the + given SoC + +Example: + + intc: interrupt-controller@e000e100 { + compatible = "arm,nvic"; + #interrupt-cells = <2>; + #address-cells = <1>; + interrupt-controller; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <4>; + };