From patchwork Sat Mar 18 04:15:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 95440 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp63683qgd; Fri, 17 Mar 2017 21:16:12 -0700 (PDT) X-Received: by 10.99.52.202 with SMTP id b193mr17424450pga.131.1489810572076; Fri, 17 Mar 2017 21:16:12 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m77si7492338pfk.46.2017.03.17.21.16.11; Fri, 17 Mar 2017 21:16:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751179AbdCREQK (ORCPT + 7 others); Sat, 18 Mar 2017 00:16:10 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:35453 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750990AbdCREQI (ORCPT ); Sat, 18 Mar 2017 00:16:08 -0400 Received: by mail-pg0-f51.google.com with SMTP id b129so51964769pgc.2 for ; Fri, 17 Mar 2017 21:15:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=l1zc5+dsUqPP2ywdyjKzD/sjpIqI4QKNTKy+5/4IEzo=; b=HHFhNeQZrFTXSy9U/Du24WQ/gv2WMKAmlT9ANEwwtYe/sbLJsPS2S9k52mI0iS4g+N 4+giGWt8uUWlg5QYomJ37Kp1CZyrwokrWGPZvZNPKTnCO7y36xnCH4Kv6t1gCh+MMkM/ i8f/lfIeE+zlyjTKtbUdmICbWbfAJZJKnUsPs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=l1zc5+dsUqPP2ywdyjKzD/sjpIqI4QKNTKy+5/4IEzo=; b=tVGureklfETZwedsQfV5Qb6U56H1Lu9e0HI7jV+GuUesogQOK2NXbUhBL9S9JKawtY lYYv6k3i7MScjnpNrAnqk5Xz8KqyzJH2pZ524Xfy25OM6eRxPbrPrgZK5KHtvS0u6Bmj oommGTGtBv3E2+ICv932ymtVi3K/UmGUMDivzOVzeP4ModyxnDGAUo0KiSuulCUeCC9x HmsJ5bKLTNfq8Pi/7Bh8t3oc65JbJqxmrxm1dtoE4aEnLZiUTgM/aeKP8suZ45X5gBRH /E5cBQLC36DcX6Hn24N/XOH8b01ckOMGcXRB5s1gu7xInUo0ZGC19qsELgEqPOcH0Lwo +dlA== X-Gm-Message-State: AFeK/H2uvwYbPpCDXHTYu71wSZJS0lU9wZNLjO04ucSx5Kb+3qYeEP5E00E5BvCK7qdviJge X-Received: by 10.99.42.78 with SMTP id q75mr19645892pgq.144.1489810527762; Fri, 17 Mar 2017 21:15:27 -0700 (PDT) Received: from localhost.localdomain (ip68-111-223-48.sd.sd.cox.net. [68.111.223.48]) by smtp.gmail.com with ESMTPSA id l17sm19512678pfg.62.2017.03.17.21.15.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Mar 2017 21:15:27 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Cc: Stephen Boyd , Rob Herring , Mark Rutland , David Brown , Srinivas Kandagatla , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/3] firmware: qcom: scm: Expose secure IO service Date: Fri, 17 Mar 2017 21:15:21 -0700 Message-Id: <20170318041523.29757-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The secure IO service provides operations for reading and writing secure memory from non-secure mode, expose this API through SCM. Signed-off-by: Bjorn Andersson --- 32-bit version is untested. drivers/firmware/qcom_scm-32.c | 11 +++++++++++ drivers/firmware/qcom_scm-64.c | 31 +++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.c | 12 ++++++++++++ drivers/firmware/qcom_scm.h | 6 ++++++ include/linux/qcom_scm.h | 4 ++++ 5 files changed, 64 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 8ad226c60374..4284745e5516 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -578,3 +578,14 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) return ret ? : le32_to_cpu(scm_ret); } + +int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr) +{ + return qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr); +} + +int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) +{ + return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, + addr, val); +} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index c9332590e8c6..eb92e67e9e41 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -381,3 +381,34 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) return ret ? : res.a1; } + +int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + int ret; + + desc.args[0] = addr; + desc.arginfo = QCOM_SCM_ARGS(1); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, + &desc, &res); + + return ret < 0 ? ret : res.a0; +} + +int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + int ret; + + desc.args[0] = addr; + desc.args[1] = val; + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, + &desc, &res); + + return ret ? : res.a0; +} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index d987bcc7489d..7a443e3afb6a 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -315,6 +315,18 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = { .deassert = qcom_scm_pas_reset_deassert, }; +int qcom_scm_io_readl(phys_addr_t addr) +{ + return __qcom_scm_io_readl(__scm->dev, addr); +} +EXPORT_SYMBOL(qcom_scm_io_readl); + +int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) +{ + return __qcom_scm_io_writel(__scm->dev, addr, val); +} +EXPORT_SYMBOL(qcom_scm_io_writel); + /** * qcom_scm_is_available() - Checks if SCM is available */ diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 6a0f15469344..327d5e0a1ec3 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -30,6 +30,12 @@ extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); #define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10 extern void __qcom_scm_cpu_power_down(u32 flags); +#define QCOM_SCM_SVC_IO 0x5 +#define QCOM_SCM_IO_READ 0x1 +#define QCOM_SCM_IO_WRITE 0x2 +extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr); +extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val); + #define QCOM_SCM_SVC_INFO 0x6 #define QCOM_IS_CALL_AVAIL_CMD 0x1 extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index d32f6f1a5225..d6e3c81907d8 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -40,6 +40,8 @@ extern int qcom_scm_pas_shutdown(u32 peripheral); extern void qcom_scm_cpu_power_down(u32 flags); extern u32 qcom_scm_get_version(void); extern int qcom_scm_set_remote_state(u32 state, u32 id); +extern int qcom_scm_io_readl(phys_addr_t addr); +extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); #else static inline int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) @@ -67,5 +69,7 @@ static inline void qcom_scm_cpu_power_down(u32 flags) {} static inline u32 qcom_scm_get_version(void) { return 0; } static inline u32 qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; } +static inline int qcom_scm_io_readl(phys_addr_t addr) { return -ENODEV; } +static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; } #endif #endif