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[2001:1868:205::9]) by mx.google.com with ESMTPS id wf7si26707371pac.46.2014.09.10.00.35.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Sep 2014 00:35:31 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XRcPo-0006zV-1J; Wed, 10 Sep 2014 07:34:08 +0000 Received: from mail-bl2on0076.outbound.protection.outlook.com ([65.55.169.76] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XRcPl-0006tc-KC for linux-arm-kernel@lists.infradead.org; Wed, 10 Sep 2014 07:34:06 +0000 Received: from BY2PR03CA075.namprd03.prod.outlook.com (10.141.249.48) by DM2PR03MB366.namprd03.prod.outlook.com (10.141.55.18) with Microsoft SMTP Server (TLS) id 15.0.1024.12; Wed, 10 Sep 2014 07:33:42 +0000 Received: from BY2FFO11FD033.protection.gbl (2a01:111:f400:7c0c::109) by BY2PR03CA075.outlook.office365.com (2a01:111:e400:2c5d::48) with Microsoft SMTP Server (TLS) id 15.0.1024.12 via Frontend Transport; Wed, 10 Sep 2014 07:33:42 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD033.mail.protection.outlook.com (10.1.14.218) with Microsoft SMTP Server (TLS) id 15.0.1019.14 via Frontend Transport; Wed, 10 Sep 2014 07:33:42 +0000 Received: from dragon ([10.192.185.80]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s8A7XcEb022312; Wed, 10 Sep 2014 00:33:39 -0700 Date: Wed, 10 Sep 2014 15:33:35 +0800 From: Shawn Guo To: "Anson.Huang@freescale.com" Subject: Re: [PATCH V2 3/3] ARM: imx: source gpt per clk from OSC for system timer Message-ID: <20140910073333.GC22579@dragon> References: <1409887606-22388-1-git-send-email-b20788@freescale.com> <1409887606-22388-4-git-send-email-b20788@freescale.com> <5E619FDB-56BB-486E-B627-9D2A9D4F9F54@freescale.com> MIME-Version: 1.0 In-Reply-To: <5E619FDB-56BB-486E-B627-9D2A9D4F9F54@freescale.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Matching-Connectors: 130548080225029098; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009019)(6009001)(448002)(24454002)(51704005)(199003)(189002)(68736004)(19580405001)(83322001)(19580395003)(84676001)(6806004)(85306004)(92566001)(50466002)(92726001)(44976005)(83506001)(575784001)(93886004)(86362001)(74502001)(90102001)(2501002)(87936001)(81342001)(47776003)(74662001)(31966008)(20776003)(97736003)(64706001)(21056001)(33716001)(54356999)(97756001)(80022001)(81542001)(26826002)(77982001)(85852003)(76176999)(46102001)(102836001)(95666004)(33656002)(106466001)(4396001)(110136001)(57986006)(83072002)(2371004)(76482001)(2351001)(46406003)(85326001)(50986999)(79102001)(107046002)(104016003)(99396002)(23726002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM2PR03MB366; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 033054F29A Received-SPF: PermError (protection.outlook.com: domain of linaro.org used an invalid SPF mechanism) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140910_003405_827664_97E02518 X-CRM114-Status: GOOD ( 20.15 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [65.55.169.76 listed in list.dnswl.org] -1.8 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [65.55.169.76 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record Cc: "devicetree@vger.kernel.org" , Fabio Estevam , "linux-arm-kernel@lists.infradead.org" , Sascha Hauer X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shawn.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Content-Disposition: inline On Fri, Sep 05, 2014 at 12:58:28PM +0000, Anson.Huang@freescale.com wrote: > >> @@ -312,10 +318,26 @@ static void __init _mxc_timer_init(int irq, > >> __raw_writel(0, timer_base + MXC_TCTL); > >> __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ > >> > >> - if (timer_is_v2()) > >> - tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; > >> - else > >> + if (timer_is_v2()) { > >> + if (((cpu_is_imx6q() && imx_get_soc_revision() > > >> + IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl() || > >> + cpu_is_imx6sx()) && (clk_get_rate(clk_per) == > >> + V2_TIMER_RATE_OSC_DIV8)) { > >> + tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR | > >> + V2_TCTL_WAITEN | MXC_TCTL_TEN; > >> + if (cpu_is_imx6dl() || cpu_is_imx6sx()) { > >> + /* 24 / 8 = 3 MHz */ > >> + tprer_val = 7 << V2_TPRER_PRE24M; > >> + __raw_writel(tprer_val, timer_base + MXC_TPRER); > >> + tctl_val |= V2_TCTL_24MEN; > >> + } > >> + } else { > >> + tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | > >> + V2_TCTL_WAITEN | MXC_TCTL_TEN; > >> + } > >> + } else { > >> tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; > >> + } > > > > Can this block be rearranged a bit so that it becomes easier to read? > > I have to consider v1, v2, and on v2, MX6Q's implementation is different from MX6DL and MX6SX, MX6SL has its special implementation, and MX6Q has difference between TO1.0 and other TOs, also, we have to consider the old dtb case. So, there are more than 6 different cases we need to consider, I thought it was the best way I can figure out, could you advice if you have better idea? [The lines should be wrapped around 70 columns] I'm also a bit concerned by the readability of the code. Can we reasonably assume it must be V2_TCTL_CLK_OSC_DIV8 case if clk_get_rate(clk_per) returns 3000000? In that case, the code can be simplified a bit, something like below. Is it going to work? Shawn @@ -349,9 +365,13 @@ static void __init mxc_timer_init_dt(struct device_node *np) WARN_ON(!timer_base); irq = irq_of_parse_and_map(np, 0); - clk_per = of_clk_get_by_name(np, "per"); clk_ipg = of_clk_get_by_name(np, "ipg"); + /* Try osc_per clock first, and fall back to per clock otherwise */ + clk_per = of_clk_get_by_name(np, "osc_per"); + if (!IS_ERR(clk_per)) + clk_per = of_clk_get_by_name(np, "per"); + _mxc_timer_init(irq, clk_per, clk_ipg); } CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 4ee6e77a0fdf..3f0401e27b38 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -245,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); + clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); if (cpu_is_imx6dl()) { clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); @@ -469,6 +470,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); + /* + * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it + * to clock gpt_ipg_per to ease the gpt driver code. + */ + if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) + clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; + if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index bf92e5a351c0..c0ad839516b0 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -312,10 +317,21 @@ static void __init _mxc_timer_init(int irq, __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - if (timer_is_v2()) - tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - else + if (timer_is_v2()) { + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { /* Is the assumption corrrect ??? */ + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + if (cpu_is_imx6dl() || cpu_is_imx6sx()) { + /* 24 / 8 = 3 MHz */ + __raw_writel(7 << V2_TPRER_PRE24M, timer_base + MXC_TPRER); + tctl_val |= V2_TCTL_24MEN; + } + } else { + tctl_val |= V2_TCTL_CLK_PER; + } + } else { tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + } __raw_writel(tctl_val, timer_base + MXC_TCTL);