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Fri, 12 Jan 2024 05:40:50 -0600 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , Srinivas Goud Subject: [PATCH RESEND v7 1/3] dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property Date: Fri, 12 Jan 2024 17:07:31 +0530 Message-ID: <1705059453-29099-2-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1705059453-29099-1-git-send-email-srinivas.goud@amd.com> References: <1705059453-29099-1-git-send-email-srinivas.goud@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|DS0PR12MB9397:EE_ X-MS-Office365-Filtering-Correlation-Id: 5523c5c6-f365-4abe-8233-08dc136356eb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: i58WTts3x8YVFGn8+zeIG0HI7qsByNAR8k0/n8WhuT7upfmQDWGTS5pv0rNjuTwcioAmoD1DWddSyyspFFGgXHAk9LVAeTxzR8kJk+mpS7bB4tbDQ0DvnGMLK/RwmW2AIeDKmvClrfzQSvoMm2LL+EsadvkOB73+IqY5ejG+ZPak2Lk1GqDSVVWBytOiE+EC65as6cu7vL/Rj4+pUgVidQQVb4v47krTayK2TLdMYRQ+8Dk9eedzSYGPvKjFAxu+/YupqsrzNyXB8VAyczCX2ZD5bIajOXthwZG5QMFfQ+wk8r6UOB5HPnTXojgiB8YhHtKDyMYtjZ53GTIrWJfaj/SRJZNoZtKFTaFceWfDH4rLDZSdeDLa4C2zc3Q7zv8T83XDqG4hrto8xlpypf+j/Xowk62B0H8jrJdC0UAQ5TkBQ15QiTg9XHvKW/imXFzoCMwiMhhLGwUyk5sTlJtE20RZVmlA07EyIPRn712q5jeMgAb3u19+cb42B6FsNBo31CaUrgRCiQv6W+im+3MxPJxCNutmhX+COgQbXav0CmEhft36ugfTgCP1cj/ebsXd5E3HKMcnzJg/clcw4rj4m6nDTKm8uyLeFhO0AZCMKc4PFS1a1pSaZsKnb/3IA3BOgxXDtyrX/H446B+KQHMtWYUO2mLugKWCKYnKdd9tDdMmW3jQZ27DtRtK3komUfqDVbrvQJB7mvjRCDq6LDEnIPlqMwqbc9lZNWHBGe3yu9N+sw72F8R5NdoH6KPA5REqhjSRqdWjh+bKXnSiQHpUYoPh4zirLBEGoSp1KN2IV6N87r7hJpQDkS/gbOofkDXhatkNrGdGjoviLunZ24I5oQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9397 ECC feature added to CAN TX_OL, TX_TL and RX FIFOs of Xilinx AXI CAN Controller. ECC is an IP configuration option where counter registers are added in IP for 1bit/2bit ECC errors. 'xlnx,has-ecc' is an optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud Acked-by: Conor Dooley --- Changes in v7: None Changes in v6: Update commit description Add Acked-by tag Changes in v5: Update property description Changes in v4: Fix binding check warning Update property description Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..8d4e5af 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = ; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - |