From patchwork Thu Jul 6 09:23:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 700467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88B2DEB64D9 for ; Thu, 6 Jul 2023 09:24:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231923AbjGFJYf (ORCPT ); Thu, 6 Jul 2023 05:24:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229721AbjGFJYe (ORCPT ); Thu, 6 Jul 2023 05:24:34 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6718D1BDC; Thu, 6 Jul 2023 02:24:11 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3668oqCq002049; Thu, 6 Jul 2023 09:23:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=sPxtzS8ZdDMvMvUNG1B/LCdbc+PcEj/xVnlEV0ATJ+I=; b=RaY3kft6QXW3caXAthZs9O36zJUkCpBNezcPKfT5v2gK6TUSirGdhujXIebFetd0oVQO fDagkMUBAVXkoAKuN4UhHTDKC8cVaNiAb6BmUyIU1bh3bSDkg4/lBRMdvIA8OSOk7V4Q LhDlX9kZJh88De4VgKS9qgbbaLRgaW6XqIgbWChelNrQqtWkPVuyVFd+gPYGknX/RRoA EgTxoNtI0xIP0vjTwo7H8EmFIGaRrB4dcnnL2Kq1dBu7xR9XjCjhaU9O+gdnixyDc9dP bQ7zxnia/7KUI6NwKdvg1lJDNJpwrpr3PJ+jzSSBe7NW66srZSGgtMAqBrIYE0N6aRDN sQ== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rn152k8ex-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 06 Jul 2023 09:23:54 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3669NoLR019312; Thu, 6 Jul 2023 09:23:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3rjd7ky1dc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 06 Jul 2023 09:23:50 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3669No2P019302; Thu, 6 Jul 2023 09:23:50 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3669Nodh019297; Thu, 06 Jul 2023 09:23:50 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id A92FE5FCD; Thu, 6 Jul 2023 14:53:49 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, Rohit Agarwal Subject: [PATCH 1/2] ARM: dts: qcom: Update the PD macros in dts Date: Thu, 6 Jul 2023 14:53:47 +0530 Message-Id: <1688635428-25127-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1688635428-25127-1-git-send-email-quic_rohiagar@quicinc.com> References: <1688635428-25127-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GR9-Ld7BudleUl1ApwyS1eb9-b07ADkp X-Proofpoint-ORIG-GUID: GR9-Ld7BudleUl1ApwyS1eb9-b07ADkp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-06_06,2023-07-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 clxscore=1015 mlxlogscore=326 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307060082 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the PD macros according to the new macros. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 6 +++--- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 313a726..1e12b3f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -761,7 +761,7 @@ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8226_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index df3cd9c..435570c 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -56,7 +56,7 @@ reg = <0x0>; enable-method = "psci"; clocks = <&apcs>; - power-domains = <&rpmhpd SDX55_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; power-domain-names = "rpmhpd"; operating-points-v2 = <&cpu_opp_table>; }; @@ -552,8 +552,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SDX55_CX>, - <&rpmhpd SDX55_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; qcom,smem-states = <&modem_smp2p_out 0>; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 1a35830..16516e9 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -57,7 +57,7 @@ reg = <0x0>; enable-method = "psci"; clocks = <&apcs>; - power-domains = <&rpmhpd SDX65_CX_AO>; + power-domains = <&rpmhpd RPMHPD_CX_AO>; power-domain-names = "rpmhpd"; operating-points-v2 = <&cpu_opp_table>; }; @@ -442,8 +442,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SDX65_CX>, - <&rpmhpd SDX65_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; qcom,smem-states = <&modem_smp2p_out 0>;