From patchwork Wed Mar 16 06:17:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 552849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F29DC4332F for ; Wed, 16 Mar 2022 06:18:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353905AbiCPGTQ (ORCPT ); Wed, 16 Mar 2022 02:19:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353872AbiCPGTH (ORCPT ); Wed, 16 Mar 2022 02:19:07 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E9931019; Tue, 15 Mar 2022 23:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411471; x=1678947471; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=maD+51x3NWHkFgFw6Zs9N4k7N1djcuz3El25dj6wKtM=; b=PjsPtFPNuNsfd2oSuYZDiJ/xUQ2QliHCgNEcSlnDPDTyBaPDs42wmyuB KezMIze0qeCvn2+KPSg0jLi0SGa2QUKp2l0jEYzxKkP9u/TFazaOwqlOX kIMPldlVZBKlOByKpq0RvdllxsTjS8UwQHqyw3gV+NdNDDhwZcXqOq4qE c=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:49 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:36 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 0B0F34495; Wed, 16 Mar 2022 11:47:36 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 4/6] ARM: dts: qcom: sdx65: Add rpmpd node Date: Wed, 16 Mar 2022 11:47:25 +0530 Message-Id: <1647411447-25249-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add rpmpd node and opps for this node to the SDX65 dts. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 51 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index ba7b6c5..7e2697f 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -244,6 +245,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx65-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; };