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Sat, 22 Jan 2022 03:24:29 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v2 2/4] arm64: tegra: Add Tegra234 I2C devicetree nodes Date: Sat, 22 Jan 2022 16:53:25 +0530 Message-ID: <1642850607-20664-3-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 559eeb59-d76d-42e3-1540-08d9dd99c43a X-MS-TrafficTypeDiagnostic: DM6PR12MB5022:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZDyJPmlX95md9OwBtC0dBNFMuzDaMqtKLEzEAaQOickuWmvn+cADzu6x9oR6u31Wy/JpCrnvy0kAvY3AcGwGUBC8NMhq69iXSt3FVbyYx3jknVGe/l9mbXuyxAB/3SMjTkEC3s5e85coKAQHSQ5bGsdWH54188QTcqmNwLSoVlbQBTh2SbXpIfzA6MhYnK0GAabs6SsFTExIi4xZQFfDeKrM8V4nyxJCF9ua46duGWVBr5pmJrVxrAzjPBRzyP3/thC1T3uGUsImsC2xcSzetPaZ5ijfJu+gMadt7HHNS77FRg+xc2vgsUKrJncZFQgm63+j8YfJOwMahQ9zaHX1ElH91+nK5KDh8zhFAsCu79fmQFOmA1FUu7G3cPhUJL/d71g6UnFHzlmT5ER7T4hcDNog+Yb871LI0psYwzY6NLQCNaR6yN1AoNw1FILFzsD6Uz0sYrKbkWz1uq5nchMCjwmWAmdes94LWwGpmrJt3agl8x9bWuOi9W9oa39KBpu8Qx3CR3aEwATma90QSPZG9lIoQHwA6cawlyq7JgJPQLN78eNw8iu02l5PB9Je0RpXo5jHF3fj4vmNvwBYWUEOwCvk22X0YWzQezKgHer0s3SxiJZDX3TwAVH2GTL4xBuk1X6jMV1JHP4ZOnlD2+lGNGPCz0piLz3EJwo42bhbe9/e6p6u7CRmAwdQMmgxGRP6NS9oOeGMl9jAJjoI8JhPPj1a+UkrhTu77T44m9Irch0h53CAaz7Mtge8S11jB7ODxe2iu0l9SrLYmJFrppvb+bpxYXLhVArbGuzEbWeFaAhaAa+VVHJQa7IIXLdpoY/qVul/VJgZEgEqOs0QxEpXGgXUte4V7ApxwraofpZObzE= X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(46966006)(36840700001)(316002)(8936002)(508600001)(81166007)(336012)(70206006)(26005)(86362001)(6666004)(186003)(36756003)(426003)(40460700003)(110136005)(5660300002)(83380400001)(47076005)(36860700001)(921005)(82310400004)(4326008)(8676002)(7696005)(2616005)(356005)(70586007)(107886003)(2906002)(83996005)(2101003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2022 11:24:34.0574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 559eeb59-d76d-42e3-1540-08d9dd99c43a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5022 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 6b6f1580..c686827 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -144,6 +144,96 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3160000 0x100>; + status = "disabled"; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C1 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C1>; + reset-names = "i2c"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3180000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C3 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C3>; + reset-names = "i2c"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3190000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C4 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C4>; + reset-names = "i2c"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31b0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C6 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C6>; + reset-names = "i2c"; + }; + + dp_aux_ch2_i2c: i2c@31c0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31c0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C7 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C7>; + reset-names = "i2c"; + }; + + dp_aux_ch3_i2c: i2c@31e0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31e0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C9 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C9>; + reset-names = "i2c"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -212,6 +302,37 @@ #mbox-cells = <2>; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc240000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C2 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C2>; + reset-names = "i2c"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc250000 0x100>; + nvidia,hw-instance-id = <0x7>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C8 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C8>; + reset-names = "i2c"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0c2a0000 0x10000>;