From patchwork Wed Apr 7 17:34:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Min Li X-Patchwork-Id: 416868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91E9EC433ED for ; Wed, 7 Apr 2021 17:40:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 626C261260 for ; Wed, 7 Apr 2021 17:40:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347979AbhDGRkQ (ORCPT ); Wed, 7 Apr 2021 13:40:16 -0400 Received: from pbmsgap02.intersil.com ([192.157.179.202]:37960 "EHLO pbmsgap02.intersil.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234723AbhDGRkP (ORCPT ); Wed, 7 Apr 2021 13:40:15 -0400 Received: from pps.filterd (pbmsgap02.intersil.com [127.0.0.1]) by pbmsgap02.intersil.com (8.16.0.42/8.16.0.42) with SMTP id 137HXFmY016777; Wed, 7 Apr 2021 13:40:01 -0400 Received: from pbmxdp02.intersil.corp (pbmxdp02.pb.intersil.com [132.158.200.223]) by pbmsgap02.intersil.com with ESMTP id 37rves8cas-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 07 Apr 2021 13:40:01 -0400 Received: from pbmxdp02.intersil.corp (132.158.200.223) by pbmxdp02.intersil.corp (132.158.200.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.2176.2; Wed, 7 Apr 2021 13:40:00 -0400 Received: from localhost (132.158.202.108) by pbmxdp02.intersil.corp (132.158.200.223) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Wed, 7 Apr 2021 13:39:59 -0400 From: To: , , , CC: , , Min Li Subject: [PATCH net-next v2 2/2] misc: Add Renesas Synchronization Management Unit (SMU) support Date: Wed, 7 Apr 2021 13:34:20 -0400 Message-ID: <1617816860-3840-2-git-send-email-min.li.xe@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617816860-3840-1-git-send-email-min.li.xe@renesas.com> References: <1617816860-3840-1-git-send-email-min.li.xe@renesas.com> X-TM-AS-MML: disable MIME-Version: 1.0 X-Proofpoint-GUID: sPur9p0_2_z8_wcK7Ff9Jh3vSuWHyx3g X-Proofpoint-ORIG-GUID: sPur9p0_2_z8_wcK7Ff9Jh3vSuWHyx3g X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-07_09:2021-04-07,2021-04-07 signatures=0 X-Proofpoint-Spam-Details: rule=junk_notspam policy=junk score=0 adultscore=0 phishscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104070119 X-Proofpoint-Spam-Reason: mlx Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Min Li This driver is developed for the IDT ClockMatrix(TM) and 82P33xxx families of timing and synchronization devices.It will be used by Renesas PTP Clock Manager for Linux (pcm4l) software to provide support to GNSS assisted partial timing support (APTS) and other networking timing functions. Current version provides kernel API's to support the following functions -set combomode to enable SYNCE clock support -read dpll's state to determine if the dpll is locked to the GNSS channel -read dpll's ffo (fractional frequency offset) in ppqt Signed-off-by: Min Li --- Change log -rebase change to linux-next tree -remove uncessary condition checks suggested by Greg -fix compile error for x86_64 -register device through misc_register suggested by Greg drivers/misc/Kconfig | 9 ++ drivers/misc/Makefile | 2 + drivers/misc/rsmu_cdev.c | 266 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/misc/rsmu_cdev.h | 74 +++++++++++++ drivers/misc/rsmu_cm.c | 166 +++++++++++++++++++++++++++++ drivers/misc/rsmu_sabre.c | 133 +++++++++++++++++++++++ include/uapi/linux/rsmu.h | 64 +++++++++++ 7 files changed, 714 insertions(+) create mode 100644 drivers/misc/rsmu_cdev.c create mode 100644 drivers/misc/rsmu_cdev.h create mode 100644 drivers/misc/rsmu_cm.c create mode 100644 drivers/misc/rsmu_sabre.c create mode 100644 include/uapi/linux/rsmu.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f532c59..49b523a 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -445,6 +445,15 @@ config HISI_HIKEY_USB switching between the dual-role USB-C port and the USB-A host ports using only one USB controller. +config RSMU + tristate "Renesas Synchronization Management Unit (SMU)" + help + This option enables support for the IDT ClockMatrix(TM) and 82P33xxx + families of timing and synchronization devices. It will be used by + Renesas PTP Clock Manager for Linux (pcm4l) software to provide support + for GNSS assisted partial timing support (APTS) and other networking + timing functions. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 99b6f15..21b8ed4 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -56,3 +56,5 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o +rsmu-objs := rsmu_cdev.o rsmu_cm.o rsmu_sabre.o +obj-$(CONFIG_RSMU) += rsmu.o diff --git a/drivers/misc/rsmu_cdev.c b/drivers/misc/rsmu_cdev.c new file mode 100644 index 0000000..f7dddcc --- /dev/null +++ b/drivers/misc/rsmu_cdev.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This driver is developed for the IDT ClockMatrix(TM) and 82P33xxx families + * of timing and synchronization devices. It will be used by Renesas PTP Clock + * Manager for Linux (pcm4l) software to provide support to GNSS assisted + * partial timing support (APTS) and other networking timing functions. + * + * Please note it must work with Renesas MFD driver to access device through + * I2C/SPI. + * + * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rsmu_cdev.h" + +#define DRIVER_NAME "rsmu" + +static struct rsmu_ops *ops_array[] = { + [RSMU_CM] = &cm_ops, + [RSMU_SABRE] = &sabre_ops, +}; + +static int +rsmu_set_combomode(struct rsmu_cdev *rsmu, void __user *arg) +{ + struct rsmu_ops *ops = rsmu->ops; + struct rsmu_combomode mode; + int err; + + if (copy_from_user(&mode, arg, sizeof(mode))) + return -EFAULT; + + if (ops->set_combomode == NULL) + return -ENOTSUPP; + + mutex_lock(rsmu->lock); + err = ops->set_combomode(rsmu, mode.dpll, mode.mode); + mutex_unlock(rsmu->lock); + + return err; +} + +static int +rsmu_get_dpll_state(struct rsmu_cdev *rsmu, void __user *arg) +{ + struct rsmu_ops *ops = rsmu->ops; + struct rsmu_get_state state_request; + u8 state; + int err; + + if (copy_from_user(&state_request, arg, sizeof(state_request))) + return -EFAULT; + + if (ops->get_dpll_state == NULL) + return -ENOTSUPP; + + mutex_lock(rsmu->lock); + err = ops->get_dpll_state(rsmu, state_request.dpll, &state); + mutex_unlock(rsmu->lock); + + state_request.state = state; + if (copy_to_user(arg, &state_request, sizeof(state_request))) + return -EFAULT; + + return err; +} + +static int +rsmu_get_dpll_ffo(struct rsmu_cdev *rsmu, void __user *arg) +{ + struct rsmu_ops *ops = rsmu->ops; + struct rsmu_get_ffo ffo_request; + int err; + + if (copy_from_user(&ffo_request, arg, sizeof(ffo_request))) + return -EFAULT; + + if (ops->get_dpll_ffo == NULL) + return -ENOTSUPP; + + mutex_lock(rsmu->lock); + err = ops->get_dpll_ffo(rsmu, ffo_request.dpll, &ffo_request); + mutex_unlock(rsmu->lock); + + if (copy_to_user(arg, &ffo_request, sizeof(ffo_request))) + return -EFAULT; + + return err; +} + +static struct rsmu_cdev *file2rsmu(struct file *file) +{ + return container_of(file->private_data, struct rsmu_cdev, miscdev); +} + +static int +rsmu_open(struct inode *iptr, struct file *fptr) +{ + return 0; +} + +static int +rsmu_release(struct inode *iptr, struct file *fptr) +{ + return 0; +} + +static long +rsmu_ioctl(struct file *fptr, unsigned int cmd, unsigned long data) +{ + struct rsmu_cdev *rsmu = file2rsmu(fptr); + void __user *arg = (void __user *)data; + int err = 0; + + switch (cmd) { + case RSMU_SET_COMBOMODE: + err = rsmu_set_combomode(rsmu, arg); + break; + case RSMU_GET_STATE: + err = rsmu_get_dpll_state(rsmu, arg); + break; + case RSMU_GET_FFO: + err = rsmu_get_dpll_ffo(rsmu, arg); + break; + default: + /* Should not get here */ + dev_err(rsmu->dev, "Undefined RSMU IOCTL"); + err = -EINVAL; + break; + } + + return err; +} + +static long rsmu_compat_ioctl(struct file *fptr, unsigned int cmd, + unsigned long data) +{ + return rsmu_ioctl(fptr, cmd, data); +} + +static const struct file_operations rsmu_fops = { + .owner = THIS_MODULE, + .open = rsmu_open, + .release = rsmu_release, + .unlocked_ioctl = rsmu_ioctl, + .compat_ioctl = rsmu_compat_ioctl, +}; + +static int rsmu_init_ops(struct rsmu_cdev *rsmu) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ops_array); i++) + if (ops_array[i]->type == rsmu->type) + break; + + if (i == ARRAY_SIZE(ops_array)) + return -EINVAL; + + rsmu->ops = ops_array[i]; + return 0; +} + +static int +rsmu_probe(struct platform_device *pdev) +{ + struct rsmu_pdata *pdata = dev_get_platdata(&pdev->dev); + struct rsmu_cdev *rsmu; + int err; + + rsmu = devm_kzalloc(&pdev->dev, sizeof(*rsmu), GFP_KERNEL); + if (!rsmu) + return -ENOMEM; + + rsmu->dev = &pdev->dev; + rsmu->mfd = pdev->dev.parent; + rsmu->type = pdata->type; + rsmu->lock = pdata->lock; + rsmu->index = pdata->index; + + /* Save driver private data */ + platform_set_drvdata(pdev, rsmu); + + /* Initialize and register the miscdev */ + rsmu->miscdev.minor = MISC_DYNAMIC_MINOR; + rsmu->miscdev.fops = &rsmu_fops; + snprintf(rsmu->name, sizeof(rsmu->name), "rsmu%d", rsmu->index); + rsmu->miscdev.name = rsmu->name; + err = misc_register(&rsmu->miscdev); + if (err) { + dev_err(rsmu->dev, "Unable to register device\n"); + return -ENODEV; + } + + err = rsmu_init_ops(rsmu); + if (err) { + dev_err(rsmu->dev, "Unknown SMU type %d", rsmu->type); + return err; + } + + dev_info(rsmu->dev, "Probe %s successful\n", rsmu->name); + return 0; +} + +static int +rsmu_remove(struct platform_device *pdev) +{ + struct rsmu_cdev *rsmu = platform_get_drvdata(pdev); + + misc_deregister(&rsmu->miscdev); + + return 0; +} + +static const struct platform_device_id rsmu_id_table[] = { + { "rsmu-cdev0", }, + { "rsmu-cdev1", }, + { "rsmu-cdev2", }, + { "rsmu-cdev3", }, + {} +}; +MODULE_DEVICE_TABLE(platform, rsmu_id_table); + +static struct platform_driver rsmu_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = rsmu_probe, + .remove = rsmu_remove, + .id_table = rsmu_id_table, +}; + +static int __init rsmu_init(void) +{ + int err; + + err = platform_driver_register(&rsmu_driver); + if (err < 0) + pr_err("Unabled to register %s platform driver", DRIVER_NAME); + + return err; +} + +static void __exit rsmu_exit(void) +{ + platform_driver_unregister(&rsmu_driver); +} + +module_init(rsmu_init); +module_exit(rsmu_exit); + +MODULE_DESCRIPTION("Renesas SMU character device driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/rsmu_cdev.h b/drivers/misc/rsmu_cdev.h new file mode 100644 index 0000000..5710929 --- /dev/null +++ b/drivers/misc/rsmu_cdev.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This driver is developed for the IDT ClockMatrix(TM) of + * timing and synchronization devices. + * + * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. + */ +#ifndef __LINUX_RSMU_CDEV_H +#define __LINUX_RSMU_CDEV_H + +#include + +struct rsmu_ops; + +/** + * struct rsmu_cdev - Driver data for RSMU character device + * @name: rsmu device name + * @dev: pointer to platform device + * @mfd: pointer to MFD device + * @miscdev: character device handle + * @lock: mutex to protect operations from being interrupted + * @type: rsmu device type + * @ops: rsmu device methods + * @index: rsmu device index + */ +struct rsmu_cdev { + char name[16]; + struct device *dev; + struct device *mfd; + struct miscdevice miscdev; + struct mutex *lock; + enum rsmu_type type; + struct rsmu_ops *ops; + u8 index; +}; + +extern struct rsmu_ops cm_ops; +extern struct rsmu_ops sabre_ops; + +struct rsmu_ops { + enum rsmu_type type; + int (*set_combomode)(struct rsmu_cdev *rsmu, u8 dpll, u8 mode); + int (*get_dpll_state)(struct rsmu_cdev *rsmu, u8 dpll, u8 *state); + int (*get_dpll_ffo)(struct rsmu_cdev *rsmu, u8 dpll, + struct rsmu_get_ffo *ffo); +}; + +/** + * Enumerated type listing DPLL combination modes + */ +enum rsmu_dpll_combomode { + E_COMBOMODE_CURRENT = 0, + E_COMBOMODE_FASTAVG, + E_COMBOMODE_SLOWAVG, + E_COMBOMODE_HOLDOVER, + E_COMBOMODE_MAX +}; + +/** + * An id used to identify the respective child class states. + */ +enum rsmu_class_state { + E_SRVLOINITIALSTATE = 0, + E_SRVLOUNQUALIFIEDSTATE = 1, + E_SRVLOLOCKACQSTATE = 2, + E_SRVLOFREQUENCYLOCKEDSTATE = 3, + E_SRVLOTIMELOCKEDSTATE = 4, + E_SRVLOHOLDOVERINSPECSTATE = 5, + E_SRVLOHOLDOVEROUTOFSPECSTATE = 6, + E_SRVLOFREERUNSTATE = 7, + E_SRVNUMBERLOSTATES = 8, + E_SRVLOSTATEINVALID = 9, +}; +#endif diff --git a/drivers/misc/rsmu_cm.c b/drivers/misc/rsmu_cm.c new file mode 100644 index 0000000..d5af624 --- /dev/null +++ b/drivers/misc/rsmu_cm.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This driver is developed for the IDT ClockMatrix(TM) of + * timing and synchronization devices. + * + * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. + */ +#include +#include +#include +#include +#include +#include +#include + +#include "rsmu_cdev.h" + +static int rsmu_cm_set_combomode(struct rsmu_cdev *rsmu, u8 dpll, u8 mode) +{ + u16 dpll_ctrl_n; + u8 cfg; + int err; + + switch (dpll) { + case 0: + dpll_ctrl_n = DPLL_CTRL_0; + break; + case 1: + dpll_ctrl_n = DPLL_CTRL_1; + break; + case 2: + dpll_ctrl_n = DPLL_CTRL_2; + break; + case 3: + dpll_ctrl_n = DPLL_CTRL_3; + break; + case 4: + dpll_ctrl_n = DPLL_CTRL_4; + break; + case 5: + dpll_ctrl_n = DPLL_CTRL_5; + break; + case 6: + dpll_ctrl_n = DPLL_CTRL_6; + break; + case 7: + dpll_ctrl_n = DPLL_CTRL_7; + break; + default: + return -EINVAL; + } + + if (mode >= E_COMBOMODE_MAX) + return -EINVAL; + + err = rsmu_read(rsmu->mfd, dpll_ctrl_n + DPLL_CTRL_COMBO_MASTER_CFG, + &cfg, sizeof(cfg)); + if (err) + return err; + + /* Only need to enable/disable COMBO_MODE_HOLD. */ + if (mode) + cfg |= COMBO_MASTER_HOLD; + else + cfg &= ~COMBO_MASTER_HOLD; + + return rsmu_write(rsmu->mfd, dpll_ctrl_n + DPLL_CTRL_COMBO_MASTER_CFG, + &cfg, sizeof(cfg)); +} + +static int rsmu_cm_get_dpll_state(struct rsmu_cdev *rsmu, u8 dpll, u8 *state) +{ + u8 cfg; + int err; + + /* 8 is sys dpll */ + if (dpll > 8) + return -EINVAL; + + err = rsmu_read(rsmu->mfd, + STATUS + DPLL0_STATUS + dpll, + &cfg, sizeof(cfg)); + if (err) + return err; + + switch (cfg & DPLL_STATE_MASK) { + case DPLL_STATE_FREERUN: + *state = E_SRVLOUNQUALIFIEDSTATE; + break; + case DPLL_STATE_LOCKACQ: + case DPLL_STATE_LOCKREC: + *state = E_SRVLOLOCKACQSTATE; + break; + case DPLL_STATE_LOCKED: + *state = E_SRVLOTIMELOCKEDSTATE; + break; + case DPLL_STATE_HOLDOVER: + *state = E_SRVLOHOLDOVERINSPECSTATE; + break; + default: + *state = E_SRVLOSTATEINVALID; + break; + } + + return 0; +} + +static int rsmu_cm_get_dpll_ffo(struct rsmu_cdev *rsmu, u8 dpll, + struct rsmu_get_ffo *ffo) +{ + u8 buf[8] = {0}; + s64 fcw = 0; + u16 dpll_filter_status; + int err; + + switch (dpll) { + case 0: + dpll_filter_status = DPLL0_FILTER_STATUS; + break; + case 1: + dpll_filter_status = DPLL1_FILTER_STATUS; + break; + case 2: + dpll_filter_status = DPLL2_FILTER_STATUS; + break; + case 3: + dpll_filter_status = DPLL3_FILTER_STATUS; + break; + case 4: + dpll_filter_status = DPLL4_FILTER_STATUS; + break; + case 5: + dpll_filter_status = DPLL5_FILTER_STATUS; + break; + case 6: + dpll_filter_status = DPLL6_FILTER_STATUS; + break; + case 7: + dpll_filter_status = DPLL7_FILTER_STATUS; + break; + case 8: + dpll_filter_status = DPLLSYS_FILTER_STATUS; + break; + default: + return -EINVAL; + } + + err = rsmu_read(rsmu->mfd, STATUS + dpll_filter_status, buf, 6); + if (err) + return err; + + /* Convert to frequency control word */ + fcw = sign_extend64(get_unaligned_le64(buf), 47); + + /* FCW unit is 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ + ffo->ffo = fcw * 111; + + return 0; +} + +struct rsmu_ops cm_ops = { + .type = RSMU_CM, + .set_combomode = rsmu_cm_set_combomode, + .get_dpll_state = rsmu_cm_get_dpll_state, + .get_dpll_ffo = rsmu_cm_get_dpll_ffo, +}; diff --git a/drivers/misc/rsmu_sabre.c b/drivers/misc/rsmu_sabre.c new file mode 100644 index 0000000..ca32b2f --- /dev/null +++ b/drivers/misc/rsmu_sabre.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This driver is developed for the IDT 82P33XXX series of + * timing and synchronization devices. + * + * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. + */ +#include +#include +#include +#include +#include +#include +#include + +#include "rsmu_cdev.h" + +static int rsmu_sabre_set_combomode(struct rsmu_cdev *rsmu, u8 dpll, u8 mode) +{ + u16 dpll_ctrl_n; + u8 cfg; + int err; + + switch (dpll) { + case 0: + dpll_ctrl_n = DPLL1_OPERATING_MODE_CNFG; + break; + case 1: + dpll_ctrl_n = DPLL2_OPERATING_MODE_CNFG; + break; + default: + return -EINVAL; + } + + if (mode >= E_COMBOMODE_MAX) + return -EINVAL; + + err = rsmu_read(rsmu->mfd, dpll_ctrl_n, &cfg, sizeof(cfg)); + if (err) + return err; + + cfg &= ~(COMBO_MODE_MASK << COMBO_MODE_SHIFT); + cfg |= mode << COMBO_MODE_SHIFT; + + return rsmu_write(rsmu->mfd, dpll_ctrl_n, &cfg, sizeof(cfg)); +} + +static int rsmu_sabre_get_dpll_state(struct rsmu_cdev *rsmu, u8 dpll, u8 *state) +{ + u16 dpll_sts_n; + u8 cfg; + int err; + + switch (dpll) { + case 0: + dpll_sts_n = DPLL1_OPERATING_STS; + break; + case 1: + dpll_sts_n = DPLL2_OPERATING_STS; + break; + default: + return -EINVAL; + } + + err = rsmu_read(rsmu->mfd, dpll_sts_n, &cfg, sizeof(cfg)); + if (err) + return err; + + switch (cfg & OPERATING_STS_MASK) { + case DPLL_STATE_FREERUN: + *state = E_SRVLOUNQUALIFIEDSTATE; + break; + case DPLL_STATE_PRELOCKED2: + case DPLL_STATE_PRELOCKED: + *state = E_SRVLOLOCKACQSTATE; + break; + case DPLL_STATE_LOCKED: + *state = E_SRVLOTIMELOCKEDSTATE; + break; + case DPLL_STATE_HOLDOVER: + *state = E_SRVLOHOLDOVERINSPECSTATE; + break; + default: + *state = E_SRVLOSTATEINVALID; + break; + } + + return 0; +} + +static int rsmu_sabre_get_dpll_ffo(struct rsmu_cdev *rsmu, u8 dpll, + struct rsmu_get_ffo *ffo) +{ + u8 buf[8] = {0}; + s64 fcw = 0; + u16 dpll_freq_n; + int err; + + /* + * IDTDpll_GetCurrentDpllFreqOffset retrieves the FFO integrator only. + * In order to get Proportional + Integrator, use the holdover FFO with + * the filter bandwidth 0.5 Hz set by TCS file. + */ + switch (dpll) { + case 0: + dpll_freq_n = DPLL1_HOLDOVER_FREQ_CNFG; + break; + case 1: + dpll_freq_n = DPLL2_HOLDOVER_FREQ_CNFG; + break; + default: + return -EINVAL; + } + + err = rsmu_read(rsmu->mfd, dpll_freq_n, buf, 5); + if (err) + return err; + + /* Convert to frequency control word */ + fcw = sign_extend64(get_unaligned_le64(buf), 39); + + /* FCW unit is 77760 / ( 1638400 * 2^48) = 1.68615121864946 * 10^-16 */ + ffo->ffo = div_s64(fcw * 168615, 1000); + + return 0; +} + +struct rsmu_ops sabre_ops = { + .type = RSMU_SABRE, + .set_combomode = rsmu_sabre_set_combomode, + .get_dpll_state = rsmu_sabre_get_dpll_state, + .get_dpll_ffo = rsmu_sabre_get_dpll_ffo, +}; diff --git a/include/uapi/linux/rsmu.h b/include/uapi/linux/rsmu.h new file mode 100644 index 0000000..02c9e38 --- /dev/null +++ b/include/uapi/linux/rsmu.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* + * Driver for the IDT ClockMatrix(TM) and 82p33xxx families of + * timing and synchronization devices. + * + * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. + */ + +#ifndef __UAPI_LINUX_RSMU_CDEV_H +#define __UAPI_LINUX_RSMU_CDEV_H + +#include +#include + +/* Set dpll combomode */ +struct rsmu_combomode { + __u8 dpll; + __u8 mode; +}; + +/* Get dpll state */ +struct rsmu_get_state { + __u8 dpll; + __u8 state; +}; + +/* Get dpll ffo (fractional frequency offset) in ppqt*/ +struct rsmu_get_ffo { + __u8 dpll; + __s64 ffo; +}; + +/* + * RSMU IOCTL List + */ +#define RSMU_MAGIC '?' + +/** + * @Description + * ioctl to set SMU combo mode. + * + * @Parameters + * pointer to struct rsmu_combomode that contains dpll combomode setting + */ +#define RSMU_SET_COMBOMODE _IOW(RSMU_MAGIC, 1, struct rsmu_combomode) + +/** + * @Description + * ioctl to get SMU dpll state. + * + * @Parameters + * pointer to struct rsmu_get_state that contains dpll state + */ +#define RSMU_GET_STATE _IOR(RSMU_MAGIC, 2, struct rsmu_get_state) + +/** + * @Description + * ioctl to get SMU dpll ffo. + * + * @Parameters + * pointer to struct rsmu_get_ffo that contains dpll ffo in ppqt + */ +#define RSMU_GET_FFO _IOR(RSMU_MAGIC, 3, struct rsmu_get_ffo) +#endif /* __UAPI_LINUX_RSMU_CDEV_H */