From patchwork Tue Mar 23 07:02:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 408413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF421C433F1 for ; Tue, 23 Mar 2021 07:04:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB6E5619BC for ; Tue, 23 Mar 2021 07:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230160AbhCWHDu (ORCPT ); Tue, 23 Mar 2021 03:03:50 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52778 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230070AbhCWHDk (ORCPT ); Tue, 23 Mar 2021 03:03:40 -0400 X-UUID: a5f47587092c4ad0a493d3357847315e-20210323 X-UUID: a5f47587092c4ad0a493d3357847315e-20210323 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 802771148; Tue, 23 Mar 2021 15:03:36 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 15:03:25 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 15:03:19 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Rob Herring , Mathias Nyman CC: Chunfeng Yun , Matthias Brugger , , , , , , Sergei Shtylyov , Eddie Hung , Nicolas Boichat Subject: [PATCH v2 13/13] arm64: dts: mt8183: update wakeup register offset Date: Tue, 23 Mar 2021 15:02:55 +0800 Message-ID: <1616482975-17841-13-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616482975-17841-1-git-send-email-chunfeng.yun@mediatek.com> References: <1616482975-17841-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use wakeup control register offset exactly, and update revision number Signed-off-by: Chunfeng Yun --- v2: modify revision format --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 80519a145f13..9ea84d636556 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -874,7 +874,7 @@ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, <&infracfg CLK_INFRA_USB>; clock-names = "sys_ck", "ref_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 0>; + mediatek,syscon-wakeup = <&pericfg 0x420 101>; #address-cells = <2>; #size-cells = <2>; ranges;