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Wed, 24 Feb 2021 05:11:13 -0800 Envelope-to: git@xilinx.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, shubhrajyoti.datta@gmail.com, miquel.raynal@bootlin.com, devel@driverdev.osuosl.org Received: from [10.140.6.59] (port=34848 helo=xhdshubhraj40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lEtwe-0001ry-50; Wed, 24 Feb 2021 05:11:12 -0800 From: Shubhrajyoti Datta To: CC: , , , , , , , , , Shubhrajyoti Datta Subject: [PATCH v10 7/9] staging: clocking-wizard: Remove the hardcoding of the clock outputs Date: Wed, 24 Feb 2021 18:40:39 +0530 Message-ID: <1614172241-17326-8-git-send-email-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1614172241-17326-1-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1614172241-17326-1-git-send-email-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 827eeefc-d62c-4240-b533-08d8d8c5bf38 X-MS-TrafficTypeDiagnostic: CY4PR02MB2392: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3276; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2021 13:11:50.0577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 827eeefc-d62c-4240-b533-08d8d8c5bf38 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT006.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2392 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The number of output clocks are configurable in the hardware. Currently the driver registers the maximum number of outputs. Fix the same by registering only the outputs that are there. Signed-off-by: Shubhrajyoti Datta --- v10: generate the names runtime. drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c index a70f09e..b0ced42 100644 --- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c +++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c @@ -517,16 +518,15 @@ static int clk_wzrd_probe(struct platform_device *pdev) } /* register div per output */ - for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) { + for (i = nr_outputs - 1; i >= 0 ; i--) { const char *clkout_name; - if (of_property_read_string_index(np, "clock-output-names", i, - &clkout_name)) { - dev_err(&pdev->dev, - "clock output name not specified\n"); - ret = -EINVAL; - goto err_rm_int_clks; + clkout_name = kasprintf(GFP_KERNEL, "%s_out%d", dev_name(&pdev->dev), i); + if (!clkout_name) { + ret = -ENOMEM; + goto err_rm_int_clk; } + if (!i) clk_wzrd->clkout[i] = clk_wzrd_register_divf (&pdev->dev, clkout_name, @@ -548,7 +548,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) if (IS_ERR(clk_wzrd->clkout[i])) { int j; - for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++) + for (j = i + 1; j < nr_outputs; j++) clk_unregister(clk_wzrd->clkout[j]); dev_err(&pdev->dev, "unable to register divider clock\n");