diff mbox series

[v2,08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding

Message ID 1610616132-8220-9-git-send-email-victor.liu@nxp.com
State New
Headers show
Series Add some DRM bridge drivers support for i.MX8qm/qxp SoCs | expand

Commit Message

Liu Ying Jan. 14, 2021, 9:22 a.m. UTC
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).

Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* Use graph schema. (Laurent)

 .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml        | 105 +++++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml

Comments

Rob Herring (Arm) Jan. 25, 2021, 9:13 p.m. UTC | #1
On Thu, Jan 14, 2021 at 05:22:06PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
> 
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v1->v2:
> * Use graph schema. (Laurent)
> 
>  .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml        | 105 +++++++++++++++++++++
>  1 file changed, 105 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> new file mode 100644
> index 00000000..187824e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
> +
> +maintainers:
> +  - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> +  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
> +  interfaces the pixel link 36-bit data output and the DSI controller’s
> +  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
> +  used in LVDS mode, to remap the pixel color codings between those modules.
> +  This module is purely combinatorial.
> +
> +properties:
> +  compatible:
> +    const: fsl,imx8qxp-pxl2dpi
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  fsl,syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: |
> +      A phandle which points to Control and Status Registers(CSR) module.

If this is the only control interface, then make it a child node of the 
phandle.

> +
> +  fsl,companion-pxl2dpi:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: |
> +      A phandle which points to companion PXL2DPI which is used by downstream
> +      LVDS Display Bridge(LDB) in split mode.
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: The PXL2DPI input port node from pixel link.
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: The PXL2DPI output port node to downstream bridge.
> +
> +    required:
> +      - port@0
> +      - port@1
> +
> +required:
> +  - compatible
> +  - power-domains
> +  - fsl,syscon
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/firmware/imx/rsrc.h>
> +    pxl2dpi {
> +        compatible = "fsl,imx8qxp-pxl2dpi";
> +        power-domains = <&pd IMX_SC_R_MIPI_0>;
> +        fsl,syscon = <&mipi_lvds_0_csr>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +                reg = <0>;
> +
> +                mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
> +                    reg = <0>;
> +                    remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
> +                };
> +
> +                mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
> +                     reg = <1>;
> +                     remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
> +                };
> +            };
> +
> +            port@1 {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +                reg = <1>;
> +
> +                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
> +                    reg = <0>;
> +                    remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
> +                };
> +
> +                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
> +                    reg = <1>;
> +                    remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
> +                };
> +            };
> +        };
> +    };
> -- 
> 2.7.4
>
Liu Ying Jan. 26, 2021, 9 a.m. UTC | #2
On Mon, 2021-01-25 at 15:13 -0600, Rob Herring wrote:
> On Thu, Jan 14, 2021 at 05:22:06PM +0800, Liu Ying wrote:

> > This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).

> > 

> > Signed-off-by: Liu Ying <victor.liu@nxp.com>

> > ---

> > v1->v2:

> > * Use graph schema. (Laurent)

> > 

> >  .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml        | 105 +++++++++++++++++++++

> >  1 file changed, 105 insertions(+)

> >  create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml

> > 

> > diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml

> > new file mode 100644

> > index 00000000..187824e

> > --- /dev/null

> > +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml

> > @@ -0,0 +1,105 @@

> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> > +%YAML 1.2

> > +---

> > +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fbridge%2Ffsl%2Cimx8qxp-pxl2dpi.yaml%23&amp;data=04%7C01%7Cvictor.liu%40nxp.com%7C39b067c8005e4019ae6f08d8c1760c31%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637472060047200709%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=u7Hv3l5h%2FwAfl31GcfBntdxDXrAAM7XBxEwitTHo2Sc%3D&amp;reserved=0

> > +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cvictor.liu%40nxp.com%7C39b067c8005e4019ae6f08d8c1760c31%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637472060047200709%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=sM%2F9h6GLwhim7LidsI6upQzly7NnZoTbal2YBGygnEE%3D&amp;reserved=0

> > +

> > +title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface

> > +

> > +maintainers:

> > +  - Liu Ying <victor.liu@nxp.com>

> > +

> > +description: |

> > +  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)

> > +  interfaces the pixel link 36-bit data output and the DSI controller’s

> > +  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module

> > +  used in LVDS mode, to remap the pixel color codings between those modules.

> > +  This module is purely combinatorial.

> > +

> > +properties:

> > +  compatible:

> > +    const: fsl,imx8qxp-pxl2dpi

> > +

> > +  power-domains:

> > +    maxItems: 1

> > +

> > +  fsl,syscon:

> > +    $ref: /schemas/types.yaml#/definitions/phandle

> > +    description: |

> > +      A phandle which points to Control and Status Registers(CSR) module.

> 

> If this is the only control interface, then make it a child node of the 

> phandle.


Will do.

Thanks,
Liu Ying

> 

> > +

> > +  fsl,companion-pxl2dpi:

> > +    $ref: /schemas/types.yaml#/definitions/phandle

> > +    description: |

> > +      A phandle which points to companion PXL2DPI which is used by downstream

> > +      LVDS Display Bridge(LDB) in split mode.

> > +

> > +  ports:

> > +    $ref: /schemas/graph.yaml#/properties/ports

> > +

> > +    properties:

> > +      port@0:

> > +        $ref: /schemas/graph.yaml#/properties/port

> > +        description: The PXL2DPI input port node from pixel link.

> > +

> > +      port@1:

> > +        $ref: /schemas/graph.yaml#/properties/port

> > +        description: The PXL2DPI output port node to downstream bridge.

> > +

> > +    required:

> > +      - port@0

> > +      - port@1

> > +

> > +required:

> > +  - compatible

> > +  - power-domains

> > +  - fsl,syscon

> > +  - ports

> > +

> > +additionalProperties: false

> > +

> > +examples:

> > +  - |

> > +    #include <dt-bindings/firmware/imx/rsrc.h>

> > +    pxl2dpi {

> > +        compatible = "fsl,imx8qxp-pxl2dpi";

> > +        power-domains = <&pd IMX_SC_R_MIPI_0>;

> > +        fsl,syscon = <&mipi_lvds_0_csr>;

> > +

> > +        ports {

> > +            #address-cells = <1>;

> > +            #size-cells = <0>;

> > +

> > +            port@0 {

> > +                #address-cells = <1>;

> > +                #size-cells = <0>;

> > +                reg = <0>;

> > +

> > +                mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {

> > +                    reg = <0>;

> > +                    remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;

> > +                };

> > +

> > +                mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {

> > +                     reg = <1>;

> > +                     remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;

> > +                };

> > +            };

> > +

> > +            port@1 {

> > +                #address-cells = <1>;

> > +                #size-cells = <0>;

> > +                reg = <1>;

> > +

> > +                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {

> > +                    reg = <0>;

> > +                    remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;

> > +                };

> > +

> > +                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {

> > +                    reg = <1>;

> > +                    remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;

> > +                };

> > +            };

> > +        };

> > +    };

> > -- 

> > 2.7.4

> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
new file mode 100644
index 00000000..187824e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
@@ -0,0 +1,105 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
+  interfaces the pixel link 36-bit data output and the DSI controller’s
+  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
+  used in LVDS mode, to remap the pixel color codings between those modules.
+  This module is purely combinatorial.
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-pxl2dpi
+
+  power-domains:
+    maxItems: 1
+
+  fsl,syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: |
+      A phandle which points to Control and Status Registers(CSR) module.
+
+  fsl,companion-pxl2dpi:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: |
+      A phandle which points to companion PXL2DPI which is used by downstream
+      LVDS Display Bridge(LDB) in split mode.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The PXL2DPI input port node from pixel link.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The PXL2DPI output port node to downstream bridge.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - power-domains
+  - fsl,syscon
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    pxl2dpi {
+        compatible = "fsl,imx8qxp-pxl2dpi";
+        power-domains = <&pd IMX_SC_R_MIPI_0>;
+        fsl,syscon = <&mipi_lvds_0_csr>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0>;
+
+                mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
+                    reg = <0>;
+                    remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
+                };
+
+                mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
+                     reg = <1>;
+                     remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
+                };
+            };
+
+            port@1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <1>;
+
+                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+                    reg = <0>;
+                    remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+                };
+
+                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+                    reg = <1>;
+                    remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+                };
+            };
+        };
+    };