From patchwork Wed Dec 23 20:35:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 352038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FAA6C43333 for ; Wed, 23 Dec 2020 20:38:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B7AD229CA for ; Wed, 23 Dec 2020 20:38:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729119AbgLWUiR (ORCPT ); Wed, 23 Dec 2020 15:38:17 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:39517 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728388AbgLWUiR (ORCPT ); Wed, 23 Dec 2020 15:38:17 -0500 Received: from localhost.localdomain ([37.4.249.194]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Mf0Nm-1kOtZs2s3O-00gXuX; Wed, 23 Dec 2020 21:35:34 +0100 From: Stefan Wahren To: Eric Anholt , Maxime Ripard , David Airlie , Daniel Vetter , Rob Herring , Nicolas Saenz Julienne Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Phil Elwell , Stefan Wahren Subject: [PATCH V2 3/4] drm/v3d: Don't clear MMU control bits on exception Date: Wed, 23 Dec 2020 21:35:13 +0100 Message-Id: <1608755714-18233-4-git-send-email-stefan.wahren@i2se.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1608755714-18233-1-git-send-email-stefan.wahren@i2se.com> References: <1608755714-18233-1-git-send-email-stefan.wahren@i2se.com> X-Provags-ID: V03:K1:tRgv/ultBc4MXu/j0X4blgyJNqQt0YNcWJ8yVfhG0vzLV4joXsS Eb+iyJQWf9Sp/D9uhMngCIBEmOFVfwUzaXCJGvVeVYeVWCOkp2JpO8zb0B/7xn0CcNXu9Cj q4rY5XawlQMwzaMvGu/o0lahtGSrkZuSQz3v5oa8zC5CFD2a1UbqpSJXqMwd7mMFniZf0w8 m9PsW8YQly5oy0qhfaIYw== X-UI-Out-Filterresults: notjunk:1; V03:K0:pXAFZhLaO7M=:vRe77kjYN1VE9h5qs4MFEh LFu2J3PKvZD+/PtCB5gEE30hmW7iXxk/uCpH7ZcZgubNGbpiFBvzLExKf8HtvzQyAqo4LBvc3 gZTSKJm1zeJWY3tWGaqzgChBTadNfbrIG8u3VEsfEkJhbTSHGTq5u7jb5nEmI7aj3zMIVUhO/ /y4o+qXsVQcS+flvXbskOa44Q+m8yvOC0N0n1MlzWWrq7y3nQhY95YxHif8SWLs+peW1MGBhr 7AP0lfiffsYVakdu8YHh1LVhqfDHPcgcsanZdF+bfHIHm1yE2dvQCQ0HZte2PMCoOR2zy3o3U RtrzwoYCu89rzO3i2BjSbZb3kobm+7+m4KhimQdwZueh80LPmIpZ8V5nK9yhRiyY7hjZVs+VP gftaSifqXsZgR1X6jq7RhIU8KpqIoFOqrTjbnQT/II5TQ7bjSn0OUkujqNSY0UmNtvwJkNoTz ToIBFlz0FQ== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Phil Elwell MMU exception conditions are reported in the V3D_MMU_CTRL register as write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any exceptions, but does so by masking out any other bits and writing the result back. There are some important control bits in that register, including MMU_ENABLE, so a safer approach is to simply write back the value just read unaltered. Signed-off-by: Phil Elwell Signed-off-by: Stefan Wahren --- drivers/gpu/drm/v3d/v3d_irq.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c index 0be2eb7..e714d53 100644 --- a/drivers/gpu/drm/v3d/v3d_irq.c +++ b/drivers/gpu/drm/v3d/v3d_irq.c @@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg) }; const char *client = "?"; - V3D_WRITE(V3D_MMU_CTL, - V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED | - V3D_MMU_CTL_PT_INVALID | - V3D_MMU_CTL_WRITE_VIOLATION)); + V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL)); if (v3d->ver >= 41) { axi_id = axi_id >> 5;