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Fri, 11 Dec 2020 01:55:06 +0000 From: Liu Ying To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, agx@sigxcpu.org, robert.chiras@nxp.com, martin.kepplinger@puri.sm Subject: [PATCH v3 4/5] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp Date: Fri, 11 Dec 2020 09:46:21 +0800 Message-Id: <1607651182-12307-5-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607651182-12307-1-git-send-email-victor.liu@nxp.com> References: <1607651182-12307-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::11) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3676.5 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?Y9JMW4ZQ6Z+RcoTZoSlqYxOczon?= =?utf-8?q?HsJ6d5whSmqpJSn9YYfVeTp9hP+2GCrR3k6TLQq3+TWUXh7jFeYivFZ4?= =?utf-8?q?L1/W6DkWXU/a1hqzzOh1wBj2gU++53H8nZooOngawWK/6PfAJdS4J5gF?= =?utf-8?q?JFfL9TbNWqVCbN8+5BAMZ7XZHGGfdiwdFzh3Xd7h3xnjb/T0Z5oH68Ut?= =?utf-8?q?P7JV8jaA0WnYoBdVVUSY+zAg+epcHNuwwXebMxTt2KDiNbnmI5ZLGbBF?= =?utf-8?q?DUXjl0eHBRwce7hlvbPzcmM3IqWIw+3GTQ/Kn4+VAoxFi9OKBlkhTIIK?= =?utf-8?q?gL7aMe3yJhjBS8Lon4yQWi+mv44XpGp0tBP5H3N5c9d+4m0sBVf4wN7c?= =?utf-8?q?QYgSmAeParNK1JMTZghz/Av/XLcT/q5WJ1TH46sMC7Epk02oOrb3vlo9?= =?utf-8?q?2inLSJzMRc0MMyn0kgYBCfLW+oFLOwz8qZRkEqq+5RYhlQny+TJZ0LIN?= =?utf-8?q?kTsUUDjY4LGL+0iBKSZe8DaNCnOhIznqp3L596MHMupq3ln2y31DK3dD?= =?utf-8?q?f4H/h0anok0e48JnRdSvTMEdaxcu2g4H3e1XiLXPZ80uyaz3snWTlmxk?= =?utf-8?q?0Ky883tox/D02FaKw5AP2XMl4m//4QoleLv+/4/VIoSFl1L2KXa6gWGq?= =?utf-8?q?pFwUES0vEh8vshKRCC0ZIzZNtYe5OSGxFlPJ3XSyOiosYLAbw/ryqTes?= =?utf-8?q?ypwFt45NfGBX6r+LTynu75VDL120bROZGX49geLOiG335vyzURwvULrl?= =?utf-8?q?h2QC4P6hBYkJxJZp6Dqn6VBQrd5fgAdbVpcry2KaxU9Cv0NmNN9CsXnE?= =?utf-8?q?Zl5L1hUWYz5//vOlpSmXjtK58KUdjsBLKv0IB2miqwgDbj+mkRGkHxf0?= =?utf-8?q?8+T8Ob4CkCDm5wObxia4/ZLOQmCQpNAJv+hux2RtPbNBstBgzi1xJ0/V?= =?utf-8?q?GENuldPs2Uoi4Wp4NO4Hgn8dBBkKzN6UkdWxkftPIhaPCo66UOVV4Ngm?= =?utf-8?q?ZwWpkDf2mocPGDxXu/OgeJns2bxXlly4w0iLXKGCAEuNu?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2020 01:55:06.3670 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-Network-Message-Id: d21a3e2a-2f14-4152-62a9-08d89d77c890 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3GoFzv2ioe5ZPTXACyTQxnJfXv48zvZCUsUrVmc8D1QnCE2HtRX1IdPtG1Efk/Kr9Ff3eQQeqGzFpCmv2ZEQtQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4045 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Mixel MIPI DPHY + LVDS PHY combo IP as found on Freescale i.MX8qxp SoC. Cc: Guido Günther Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Rob Herring Cc: NXP Linux Team Signed-off-by: Liu Ying Reviewed-by: Guido Günther --- v2->v3: * No change. v1->v2: * Add the binding for i.MX8qxp Mixel combo PHY based on the converted binding. (Guido) .../bindings/phy/mixel,mipi-dsi-phy.yaml | 41 ++++++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml index c34f2e6..786cfd7 100644 --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml @@ -14,10 +14,14 @@ description: | MIPI-DSI IP from Northwest Logic). It represents the physical layer for the electrical signals for DSI. + The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work + in either MIPI-DSI PHY mode or LVDS PHY mode. + properties: compatible: enum: - fsl,imx8mq-mipi-dphy + - fsl,imx8qxp-mipi-dphy reg: maxItems: 1 @@ -40,6 +44,11 @@ properties: "#phy-cells": const: 0 + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers(CSR) module. + power-domains: maxItems: 1 @@ -48,12 +57,38 @@ required: - reg - clocks - clock-names - - assigned-clocks - - assigned-clock-parents - - assigned-clock-rates - "#phy-cells" - power-domains +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-mipi-dphy + then: + properties: + fsl,syscon: false + + required: + - assigned-clocks + - assigned-clock-parents + - assigned-clock-rates + + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-mipi-dphy + then: + properties: + assigned-clocks: false + assigned-clock-parents: false + assigned-clock-rates: false + + required: + - fsl,syscon + additionalProperties: false examples: