From patchwork Mon Nov 23 03:48:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsin-Hsiung Wang X-Patchwork-Id: 331599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02E25C56201 for ; Mon, 23 Nov 2020 03:49:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B6C792074B for ; Mon, 23 Nov 2020 03:49:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727901AbgKWDsf (ORCPT ); Sun, 22 Nov 2020 22:48:35 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:37107 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727822AbgKWDsf (ORCPT ); Sun, 22 Nov 2020 22:48:35 -0500 X-UUID: 624b78af96af4ecfa4f3f0f87ac435ff-20201123 X-UUID: 624b78af96af4ecfa4f3f0f87ac435ff-20201123 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 32609552; Mon, 23 Nov 2020 11:48:26 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 23 Nov 2020 11:48:25 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 Nov 2020 11:48:25 +0800 From: Hsin-Hsiung Wang To: Lee Jones , Rob Herring , Matthias Brugger , Liam Girdwood , Mark Brown CC: Hsin-Hsiung Wang , , , , , Subject: [PATCH v3 6/8] regulator: mt6359: Set the enable time for LDOs Date: Mon, 23 Nov 2020 11:48:08 +0800 Message-ID: <1606103290-15034-7-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1606103290-15034-1-git-send-email-hsin-hsiung.wang@mediatek.com> References: <1606103290-15034-1-git-send-email-hsin-hsiung.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the enable time for LDOs. This patch is preparing for adding mt6359p regulator support. Signed-off-by: Hsin-Hsiung Wang Acked-by: Mark Brown --- drivers/regulator/mt6359-regulator.c | 65 ++++++++++++++++++---------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/regulator/mt6359-regulator.c b/drivers/regulator/mt6359-regulator.c index 9746e2c281ae..6ce782723eba 100644 --- a/drivers/regulator/mt6359-regulator.c +++ b/drivers/regulator/mt6359-regulator.c @@ -114,7 +114,7 @@ struct mt6359_regulator_info { #define MT6359_LDO(match, _name, _volt_table, \ _enable_reg, _enable_mask, _status_reg, \ - _vsel_reg, _vsel_mask) \ + _vsel_reg, _vsel_mask, _en_delay) \ [MT6359_ID_##_name] = { \ .desc = { \ .name = #_name, \ @@ -129,6 +129,7 @@ struct mt6359_regulator_info { .vsel_mask = _vsel_mask, \ .enable_reg = _enable_reg, \ .enable_mask = BIT(_enable_mask), \ + .enable_time = _en_delay, \ }, \ .status_reg = _status_reg, \ .qi = BIT(0), \ @@ -516,15 +517,18 @@ static struct mt6359_regulator_info mt6359_regulators[] = { MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages, MT6359_RG_LDO_VSIM1_EN_ADDR, MT6359_RG_LDO_VSIM1_EN_SHIFT, MT6359_DA_VSIM1_B_EN_ADDR, MT6359_RG_VSIM1_VOSEL_ADDR, - MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT), + MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT, + 480), MT6359_LDO("ldo_vibr", VIBR, vibr_voltages, MT6359_RG_LDO_VIBR_EN_ADDR, MT6359_RG_LDO_VIBR_EN_SHIFT, MT6359_DA_VIBR_B_EN_ADDR, MT6359_RG_VIBR_VOSEL_ADDR, - MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT), + MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT, + 240), MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages, MT6359_RG_LDO_VRF12_EN_ADDR, MT6359_RG_LDO_VRF12_EN_SHIFT, MT6359_DA_VRF12_B_EN_ADDR, MT6359_RG_VRF12_VOSEL_ADDR, - MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT), + MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT, + 120), MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359_RG_LDO_VUSB_EN_0_ADDR, MT6359_DA_VUSB_B_EN_ADDR, 3000000), MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250, @@ -539,11 +543,13 @@ static struct mt6359_regulator_info mt6359_regulators[] = { MT6359_LDO("ldo_vio18", VIO18, volt18_voltages, MT6359_RG_LDO_VIO18_EN_ADDR, MT6359_RG_LDO_VIO18_EN_SHIFT, MT6359_DA_VIO18_B_EN_ADDR, MT6359_RG_VIO18_VOSEL_ADDR, - MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT), + MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT, + 960), MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages, MT6359_RG_LDO_VCAMIO_EN_ADDR, MT6359_RG_LDO_VCAMIO_EN_SHIFT, MT6359_DA_VCAMIO_B_EN_ADDR, MT6359_RG_VCAMIO_VOSEL_ADDR, - MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT), + MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT, + 1290), MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359_RG_LDO_VCN18_EN_ADDR, MT6359_DA_VCN18_B_EN_ADDR, 1800000), MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359_RG_LDO_VFE28_EN_ADDR, @@ -551,19 +557,20 @@ static struct mt6359_regulator_info mt6359_regulators[] = { MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages, MT6359_RG_LDO_VCN13_EN_ADDR, MT6359_RG_LDO_VCN13_EN_SHIFT, MT6359_DA_VCN13_B_EN_ADDR, MT6359_RG_VCN13_VOSEL_ADDR, - MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT), + MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT, + 240), MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages, MT6359_RG_LDO_VCN33_1_EN_0_ADDR, MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR, MT6359_RG_VCN33_1_VOSEL_MASK << - MT6359_RG_VCN33_1_VOSEL_SHIFT), + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages, MT6359_RG_LDO_VCN33_1_EN_1_ADDR, MT6359_RG_LDO_VCN33_1_EN_1_SHIFT, MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR, MT6359_RG_VCN33_1_VOSEL_MASK << - MT6359_RG_VCN33_1_VOSEL_SHIFT), + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359_RG_LDO_VAUX18_EN_ADDR, MT6359_DA_VAUX18_B_EN_ADDR, 1800000), MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, @@ -579,49 +586,57 @@ static struct mt6359_regulator_info mt6359_regulators[] = { MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, MT6359_RG_LDO_VEFUSE_EN_ADDR, MT6359_RG_LDO_VEFUSE_EN_SHIFT, MT6359_DA_VEFUSE_B_EN_ADDR, MT6359_RG_VEFUSE_VOSEL_ADDR, - MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT), + MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT, + 240), MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages, MT6359_RG_LDO_VXO22_EN_ADDR, MT6359_RG_LDO_VXO22_EN_SHIFT, MT6359_DA_VXO22_B_EN_ADDR, MT6359_RG_VXO22_VOSEL_ADDR, - MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT), + MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT, + 120), MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages, MT6359_RG_LDO_VRFCK_EN_ADDR, MT6359_RG_LDO_VRFCK_EN_SHIFT, MT6359_DA_VRFCK_B_EN_ADDR, MT6359_RG_VRFCK_VOSEL_ADDR, - MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT), + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, + 480), MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359_RG_LDO_VBIF28_EN_ADDR, MT6359_DA_VBIF28_B_EN_ADDR, 2800000), MT6359_LDO("ldo_vio28", VIO28, vio28_voltages, MT6359_RG_LDO_VIO28_EN_ADDR, MT6359_RG_LDO_VIO28_EN_SHIFT, MT6359_DA_VIO28_B_EN_ADDR, MT6359_RG_VIO28_VOSEL_ADDR, - MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT), + MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT, + 240), MT6359_LDO("ldo_vemc", VEMC, vemc_voltages, MT6359_RG_LDO_VEMC_EN_ADDR, MT6359_RG_LDO_VEMC_EN_SHIFT, MT6359_DA_VEMC_B_EN_ADDR, MT6359_RG_VEMC_VOSEL_ADDR, - MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT), + MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT, + 240), MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages, MT6359_RG_LDO_VCN33_2_EN_0_ADDR, MT6359_RG_LDO_VCN33_2_EN_0_SHIFT, MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR, MT6359_RG_VCN33_2_VOSEL_MASK << - MT6359_RG_VCN33_2_VOSEL_SHIFT), + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages, MT6359_RG_LDO_VCN33_2_EN_1_ADDR, MT6359_RG_LDO_VCN33_2_EN_1_SHIFT, MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR, MT6359_RG_VCN33_2_VOSEL_MASK << - MT6359_RG_VCN33_2_VOSEL_SHIFT), + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), MT6359_LDO("ldo_va12", VA12, va12_voltages, MT6359_RG_LDO_VA12_EN_ADDR, MT6359_RG_LDO_VA12_EN_SHIFT, MT6359_DA_VA12_B_EN_ADDR, MT6359_RG_VA12_VOSEL_ADDR, - MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT), + MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT, + 240), MT6359_LDO("ldo_va09", VA09, va09_voltages, MT6359_RG_LDO_VA09_EN_ADDR, MT6359_RG_LDO_VA09_EN_SHIFT, MT6359_DA_VA09_B_EN_ADDR, MT6359_RG_VA09_VOSEL_ADDR, - MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT), + MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT, + 240), MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages, MT6359_RG_LDO_VRF18_EN_ADDR, MT6359_RG_LDO_VRF18_EN_SHIFT, MT6359_DA_VRF18_B_EN_ADDR, MT6359_RG_VRF18_VOSEL_ADDR, - MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT), + MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT, + 120), MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1100000, 6250, 0, mt_volt_range7, MT6359_RG_LDO_VSRAM_MD_EN_ADDR, MT6359_DA_VSRAM_MD_B_EN_ADDR, @@ -634,15 +649,18 @@ static struct mt6359_regulator_info mt6359_regulators[] = { MT6359_LDO("ldo_vufs", VUFS, volt18_voltages, MT6359_RG_LDO_VUFS_EN_ADDR, MT6359_RG_LDO_VUFS_EN_SHIFT, MT6359_DA_VUFS_B_EN_ADDR, MT6359_RG_VUFS_VOSEL_ADDR, - MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT), + MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT, + 1920), MT6359_LDO("ldo_vm18", VM18, volt18_voltages, MT6359_RG_LDO_VM18_EN_ADDR, MT6359_RG_LDO_VM18_EN_SHIFT, MT6359_DA_VM18_B_EN_ADDR, MT6359_RG_VM18_VOSEL_ADDR, - MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT), + MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT, + 1920), MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages, MT6359_RG_LDO_VBBCK_EN_ADDR, MT6359_RG_LDO_VBBCK_EN_SHIFT, MT6359_DA_VBBCK_B_EN_ADDR, MT6359_RG_VBBCK_VOSEL_ADDR, - MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT), + MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT, + 240), MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250, 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR, MT6359_DA_VSRAM_PROC1_B_EN_ADDR, @@ -655,7 +673,8 @@ static struct mt6359_regulator_info mt6359_regulators[] = { MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages, MT6359_RG_LDO_VSIM2_EN_ADDR, MT6359_RG_LDO_VSIM2_EN_SHIFT, MT6359_DA_VSIM2_B_EN_ADDR, MT6359_RG_VSIM2_VOSEL_ADDR, - MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT), + MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT, + 480), MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000, 1293750, 6250, 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR,