From patchwork Fri Nov 6 09:46:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 321379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DF17C5517A for ; Fri, 6 Nov 2020 09:47:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A1F3120A8B for ; Fri, 6 Nov 2020 09:47:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="C0gjzz8Q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726743AbgKFJq4 (ORCPT ); Fri, 6 Nov 2020 04:46:56 -0500 Received: from esa6.microchip.iphmx.com ([216.71.154.253]:60401 "EHLO esa6.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726846AbgKFJqz (ORCPT ); Fri, 6 Nov 2020 04:46:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604656014; x=1636192014; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=5kPPY8aoeoIt3eWzwt2rrqZVySb3GOzC6e0UsowoKcY=; b=C0gjzz8QSXov093teeaKkxISaBA7Ooo6b8XhwYOdCJy+PqRcAb1VQaNq IX2jBWA4p+MWF/9FjdoDHhHkCj7CLxpafH7hTXyFX5P7/lEykMQREkR6o 62yw3Ox5Wwvj0D/dRPZ2DlmL+hZLFjGpKMnUuBHM5L5bAV7JixOtpVnNk r3S8BZE0ivVM/AND8QMZUMk91jkb84B4yGxs6dChLf6ws6WSX4WZLKQo1 ELrFley7tVc8FGtFtqm2Cmb6+UeN2brZroPmaBJFrOwrky9EFevM5LI8Y 5kRUHcGye9kGptnXTjCnp8k+CanSIc8TETtcXuAWhQ2iWyC4dzAOqrWZy w==; IronPort-SDR: o4An7FiQKzvpe73fhd6q8JTQgB6X1YnYKGsZWnvCD8+KHR9BAqm99K9HoUK6AS5mu4DT0MFwlX xRyrOAdn6i3HARh1n+KqiyfIFF4gS3z/LyxwBBU2ed/WjF9kQeLzMa/KVlvPa7wChY5a7h9lOf SbTv+/H28jNY0F5hx9MRAhhABsLmg9f+jTLtsWzV4qUmLg6Yq1ieNfUu7L5+Sbyyx9ieJe0rLC JN1M1wOLmnihOPC0Ab7YD/VxnUL5RJdgmqhMqJ1SPoxkMr8ibWPi+xKXuFsTthl/d134xruvJf xrY= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="32680412" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:46:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:46:53 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:46:48 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , , Claudiu Beznea Subject: [PATCH v4 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT Date: Fri, 6 Nov 2020 11:46:20 +0200 Message-ID: <1604655988-353-4-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604655988-353-1-git-send-email-claudiu.beznea@microchip.com> References: <1604655988-353-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Eugen Hristev Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Suggested-by: Claudiu Beznea Signed-off-by: Eugen Hristev [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 7ef7963126b6..d3c3469d47d9 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -117,7 +117,8 @@ static const struct { .p = "cpupll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, }, + .c = 1, + .eid = PMC_CPUPLL, }, }, [PLL_ID_SYS] = { @@ -131,7 +132,8 @@ static const struct { .p = "syspll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, }, + .c = 1, + .eid = PMC_SYSPLL, }, }, [PLL_ID_DDR] = {