From patchwork Mon Sep 28 01:05:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313606 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2908938ilg; Sun, 27 Sep 2020 18:05:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwwGkqamHruweHGdqceQ6JO19thcaNW9BIaK8hfilHhCx/U0rwl8OSxUnKV+vX/RcyPrJyK X-Received: by 2002:a50:fd83:: with SMTP id o3mr12981802edt.176.1601255155473; Sun, 27 Sep 2020 18:05:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601255155; cv=none; d=google.com; s=arc-20160816; b=xriMsXpZ2bP+iYckG3Odv2j3WuShHCOiy2JGx7ppR1d8u9MsbsZZutsvOEVPP8+F8H PF45inmeV6epko5n9rp9qbJ2NX6VKHIXQws1k4j7ZGZG5KnLbnf8VT6ZMUCPyDY6uTPn dhlABCDnYzJZdnGGC7CYm/EYQSI5Fr81Es1NCY73OEA1oQ0OP4QDWcWVYn28JXzcTsho 85ud+OzPhT7VIk0i845ES+AOjewiyFcI5rXF6TnYPwigHqAo6lyDIUAcgbZ9ZGpCYiOl d3pytdv58mEtZFlmomhOdipqWjbWT6il9EzXWPx637qx5jzEkohXqc/EbpsSYlyj+mL0 Ez0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=9sTO2+6sshoR05fbn/I8S0NStuSfvzcogMkhhjaoGUk=; b=Aw2ywoQpQKrgUZ9zfU6knaIBVXJ0AC3s6SJ9Jtg3sM5RyXnJmVuE5emf6rG+fqN1b9 y/dodcCstm+qvPmcY2id2ijHL4vS300KF0q16emBp5D9x0kDcK0NAvIHM9gsebBY+WEf vbaOLE6kRCpdLFqX8EqpvIH0HDAoEVMeXr11Fh8Ul9M78kT8pYXln/W7rVHiI5w2PYuN xX5liIm1TqbW5ZRAUwHkzKS5XgFTHKUuxynWqC30LV5aHOzBjkqoZmIYGsU455oM7CEI 9KnKkUvGE9uR8KOAtqtEme0pKDRj5ChhXWhm6GKeXyxuBMa1gfZiW1CoRkJ42wrFnfYo kLdQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u15si7301922edo.55.2020.09.27.18.05.55; Sun, 27 Sep 2020 18:05:55 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726572AbgI1BFr (ORCPT + 6 others); Sun, 27 Sep 2020 21:05:47 -0400 Received: from mx.socionext.com ([202.248.49.38]:27540 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726547AbgI1BFr (ORCPT ); Sun, 27 Sep 2020 21:05:47 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 28 Sep 2020 10:05:45 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 3542B180BE1; Mon, 28 Sep 2020 10:05:45 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 28 Sep 2020 10:05:45 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 925951A0507; Mon, 28 Sep 2020 10:05:44 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 3/4] PCI: dwc: Add common iATU register support Date: Mon, 28 Sep 2020 10:05:32 +0900 Message-Id: <1601255133-17715-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601255133-17715-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-designware.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3fe859f..b6b39af 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "../../pci.h" @@ -548,11 +549,15 @@ void dw_pcie_setup(struct dw_pcie *pci) u32 val; struct device *dev = pci->dev; struct device_node *np = dev->of_node; + struct platform_device *pdev = to_platform_device(dev); if (pci->version >= 0x480A || (!pci->version && dw_pcie_iatu_unroll_enabled(pci))) { pci->iatu_unroll_enabled = true; if (!pci->atu_base) + pci->atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(pci->atu_base)) pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; } dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?