From patchwork Thu Aug 6 09:21:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 254055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13B41C38145 for ; Thu, 6 Aug 2020 11:13:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A57922D02 for ; Thu, 6 Aug 2020 11:13:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Z4lOVlI1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729047AbgHFJcW (ORCPT ); Thu, 6 Aug 2020 05:32:22 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:38463 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729028AbgHFJWr (ORCPT ); Thu, 6 Aug 2020 05:22:47 -0400 X-UUID: e2bfd24346744ad49390cd1416a776bf-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=vyt/5VZetwvfAg/d0ebCsFaxhaPADW7wXGw7LIYUkgE=; b=Z4lOVlI1B0ZYu91KgzvOWOPQZPBNJaZOhyfbdXUagsJoCpaHabDR+Y7PMwXsYRKWNKL0hkUCCdIYg9BfqgVAnwdurtTy0TPWJOkhL7xDDnT+G/bvRKcPCItE1L2dKWewZ44XfA/FE1RjMMDsECoFK9Pek+FFOZRC2/zTI/7e73U=; X-UUID: e2bfd24346744ad49390cd1416a776bf-20200806 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 900334158; Thu, 06 Aug 2020 17:22:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:22:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:22:00 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v17 11/12] arm64: dts: Add power controller device node of MT8183 Date: Thu, 6 Aug 2020 17:21:54 +0800 Message-ID: <1596705715-15320-12-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add power controller node and smi-common node for MT8183 In scpsys node, it contains clocks and regmapping of infracfg and smi-common for bus protection. And list all the power domains of MT8183 under scpsys node to show the dependency between each other through hierarchical structure. Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 123 +++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) -- 1.8.1.1.dirty diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1e03c84..4940bda 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mt8183-pinfunc.h" @@ -309,6 +310,123 @@ #interrupt-cells = <2>; }; + scpsys: power-controller@10006000 { + compatible = "mediatek,mt8183-scpsys", "syscon"; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_MFG>, + <&topckgen CLK_TOP_MUX_MM>, + <&topckgen CLK_TOP_MUX_CAM>, + <&topckgen CLK_TOP_MUX_IMG>, + <&topckgen CLK_TOP_MUX_IPU_IF>, + <&topckgen CLK_TOP_MUX_DSP>, + <&topckgen CLK_TOP_MUX_DSP1>, + <&topckgen CLK_TOP_MUX_DSP2>; + clock-names = "audio", "audio1", "audio2", "mfg", "mm", + "cam", "isp", "vpu", "vpu1", "vpu2", + "vpu3"; + infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + audio@MT8183_POWER_DOMAIN_AUDIO { + reg = ; + }; + + conn@MT8183_POWER_DOMAIN_CONN { + reg = ; + }; + + mfg_async@MT8183_POWER_DOMAIN_MFG_ASYNC { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + mfg@MT8183_POWER_DOMAIN_MFG { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + mfg_core0@MT8183_POWER_DOMAIN_MFG_CORE0 { + reg = ; + }; + + mfg_core1@MT8183_POWER_DOMAIN_MFG_CORE1 { + reg = ; + }; + + mfg_2d@MT8183_POWER_DOMAIN_MFG_2D { + reg = ; + }; + }; + }; + + disp@MT8183_POWER_DOMAIN_DISP { + reg = ; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB1>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>, + <&mmsys CLK_MM_GALS_CCU2MM>, + <&mmsys CLK_MM_GALS_IPU12MM>, + <&mmsys CLK_MM_GALS_IMG2MM>, + <&mmsys CLK_MM_GALS_CAM2MM>, + <&mmsys CLK_MM_GALS_IPU2MM>; + #address-cells = <1>; + #size-cells = <0>; + + cam@MT8183_POWER_DOMAIN_CAM { + reg = ; + clocks = <&camsys CLK_CAM_LARB6>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_SENINF>, + <&camsys CLK_CAM_CAMSV0>, + <&camsys CLK_CAM_CAMSV1>, + <&camsys CLK_CAM_CAMSV2>, + <&camsys CLK_CAM_CCU>; + }; + + isp@MT8183_POWER_DOMAIN_ISP { + reg = ; + clocks = <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_LARB2>; + }; + + vdec@MT8183_POWER_DOMAIN_VDEC { + reg = ; + }; + + vden@MT8183_POWER_DOMAIN_VENC { + reg = ; + }; + + vpu_top@MT8183_POWER_DOMAIN_VPU_TOP { + reg = ; + clocks = <&ipu_conn CLK_IPU_CONN_IPU>, + <&ipu_conn CLK_IPU_CONN_AHB>, + <&ipu_conn CLK_IPU_CONN_AXI>, + <&ipu_conn CLK_IPU_CONN_ISP>, + <&ipu_conn CLK_IPU_CONN_CAM_ADL>, + <&ipu_conn CLK_IPU_CONN_IMG_ADL>; + #address-cells = <1>; + #size-cells = <0>; + + vpu_core0@MT8183_POWER_DOMAIN_VPU_CORE0 { + reg = ; + }; + + vpu_core1@MT8183_POWER_DOMAIN_VPU_CORE1 { + reg = ; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; @@ -690,6 +808,11 @@ #clock-cells = <1>; }; + smi_common: smi@14019000 { + compatible = "mediatek,mt8183-smi-common", "syscon"; + reg = <0 0x14019000 0 0x1000>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>;