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Fri, 26 Jun 2020 05:42:07 -0700 Received: from [10.140.6.59] (helo=xhdshubhraj40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jongF-0001Wm-5O; Fri, 26 Jun 2020 05:42:07 -0700 From: Shubhrajyoti Datta To: linux-clk@vger.kernel.org Cc: sboyd@kernel.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, shubhrajyoti.datta@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, michals@xilinx.com, Shubhrajyoti Datta Subject: [PATCH v4 6/8] clk: clock-wizard: Remove the hardcoding of the clock outputs Date: Fri, 26 Jun 2020 18:11:42 +0530 Message-Id: <1593175304-4876-7-git-send-email-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1593175304-4876-1-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1593175304-4876-1-git-send-email-shubhrajyoti.datta@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT057.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5083 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The number of output clocks are configurable in the hardware. Currently the driver registers the maximum number of outputs. Fix the same by registering only the outputs that are there. Signed-off-by: Shubhrajyoti Datta --- v4: Assign output in this patch drivers/clk/clk-xlnx-clock-wizard.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index 8a7f9bb..28bbaa0 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -495,6 +495,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) const char *clk_name; struct clk_wzrd *clk_wzrd; struct resource *mem; + int outputs; struct device_node *np = pdev->dev.of_node; clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); @@ -565,6 +566,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) goto err_disable_clk; } + outputs = of_property_count_strings(np, "clock-output-names"); /* register div */ reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT; @@ -586,7 +588,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) } /* register div per output */ - for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) { + for (i = outputs - 1; i >= 0 ; i--) { const char *clkout_name; if (of_property_read_string_index(np, "clock-output-names", i, @@ -617,7 +619,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) if (IS_ERR(clk_wzrd->clkout[i])) { int j; - for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++) + for (j = i + 1; j < outputs; j++) clk_unregister(clk_wzrd->clkout[j]); dev_err(&pdev->dev, "unable to register divider clock\n");