From patchwork Thu Jun 18 08:38:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 191088 Delivered-To: patch@linaro.org Received: by 2002:a54:30ca:0:0:0:0:0 with SMTP id e10csp1125969ecs; Thu, 18 Jun 2020 01:39:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/gUAUFX4c/fLYMvFKlOPkBQhdg0UfNl0qpBQV0P4UzyQpe2oer1R5RcMxk4HksYo9wJj7 X-Received: by 2002:a50:f19d:: with SMTP id x29mr3037350edl.215.1592469539953; Thu, 18 Jun 2020 01:38:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592469539; cv=none; d=google.com; s=arc-20160816; b=YNkDJJfNma57+C8cPVcuFC80k+vc1hvNINd/AyWLT9+2wKuc0FIdx+MOsuIcC+k7pr Q8nh8i3490QPR3O0Ys7sx/6aF0wxGzR3UvepRUPiaJ4dElAhMlyrrT8kLZ1VBwfwRgN/ c+3DlKCs/2kQIMCc4Z7RaxdaNz5R4ED7e4asjPsNNfIb4y/9ys451HN+eH28MajRAjTF KwbWxfBaF7dpgYiXiuJxu31vZP2XqjLeij6c9g1ssTFs/YxuXG9Jimg/uUI82TJh3xU/ vdXyqRm0kx1S1Wp5jmsXyBiTJ0LLIqp6HE6hGuijxpFVRh8bwZJysE4PeQ604aRGCDzp Dk3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=4P4GjfjkLq9hygITUkCPD7eIs/Iyu2aXHk0ElH5z3fI=; b=mz18P9GFbyZzf+/UQ41fiw0rvjAZfpRKvQo6qLjxk5WwdJeTTYuBTxfW2dw5L/zJxu E1njkcauETScKrqeLFtHyraoQAmrP+TgVtoJrlfJ2tdJMcZFtGRep0hrtXolbMJmXoBi boXf9dMgz5SFEu4mwIdnoIUmTPubMsQYVzrwS7XWVSbi70wz6upiTYsN9Q/e/OfzsLQE KX+NFIFJahkYLDOaW9tSnk8afFH4OTZYVGBUjwCR7udIavj1HbojWcrOKj0VtfZ+bmm1 L7hCZxmqHGrLULp1bJdoEO+Zgu3R9MPI25Ks6fxIqniCJ4dmmTO07Vsa2Lpyr5mIigLh CD4g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a15si1490925ejd.215.2020.06.18.01.38.59; Thu, 18 Jun 2020 01:38:59 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728849AbgFRIic (ORCPT + 6 others); Thu, 18 Jun 2020 04:38:32 -0400 Received: from mx.socionext.com ([202.248.49.38]:19364 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728824AbgFRIi2 (ORCPT ); Thu, 18 Jun 2020 04:38:28 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:26 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id E406C60057; Thu, 18 Jun 2020 17:38:26 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:26 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 5E0AB1A12AD; Thu, 18 Jun 2020 17:38:26 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 4/6] PCI: uniphier: Add iATU register support Date: Thu, 18 Jun 2020 17:38:11 +0900 Message-Id: <1592469493-1549-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This gets iATU register area from reg property. In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 5ce2479..c37a968 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -451,6 +451,11 @@ static int uniphier_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->pci.dbi_base)) return PTR_ERR(priv->pci.dbi_base); + priv->pci.atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(priv->pci.atu_base)) + priv->pci.atu_base = NULL; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link"); priv->base = devm_ioremap_resource(dev, res); if (IS_ERR(priv->base))