From patchwork Thu May 28 09:57:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: EastL Lee X-Patchwork-Id: 199862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2160CC433E1 for ; Thu, 28 May 2020 09:57:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F35CA21475 for ; Thu, 28 May 2020 09:57:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XU5BUltN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387642AbgE1J5k (ORCPT ); Thu, 28 May 2020 05:57:40 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:29687 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2387629AbgE1J5f (ORCPT ); Thu, 28 May 2020 05:57:35 -0400 X-UUID: 7aad5b26800d4fc391914dab168756f1-20200528 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qNLHaRDt92Fy5R0FyEm9iP9GROfWqd9LmF7e4CqwFP0=; b=XU5BUltNIun+r3mRjeUxy9HDmgTHIXjk2c53rPThGHdCW1dsA413P0uDwuiE7UbHpKnHJUOQwCrj7nOuggYhMhIsm3YYpkywYlWKqyA91aiF+AvES24DX1vRpa6rAhO66WeJZ3q2AVkFcasePYdgasiT9Hu74YMIp3Rh44U3faY=; X-UUID: 7aad5b26800d4fc391914dab168756f1-20200528 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 141802822; Thu, 28 May 2020 17:57:29 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 May 2020 17:57:19 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 May 2020 17:57:19 +0800 From: EastL To: Sean Wang CC: , , , , , , , , , , EastL Subject: [PATCH v4 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings Date: Thu, 28 May 2020 17:57:09 +0800 Message-ID: <1590659832-31476-2-git-send-email-EastL.Lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1590659832-31476-1-git-send-email-EastL.Lee@mediatek.com> References: <1590659832-31476-1-git-send-email-EastL.Lee@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 6D5D9921259AA598827C15891D3DFD3FA6561D05860E5A426B9F9233B9394F702000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the devicetree bindings for MediaTek Command-Queue DMA controller which could be found on MT6779 SoC or other similar Mediatek SoCs. Signed-off-by: EastL --- .../devicetree/bindings/dma/mtk-cqdma.yaml | 100 +++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml -- 1.9.1 diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml new file mode 100644 index 0000000..045aa0c --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Command-Queue DMA controller Device Tree Binding + +maintainers: + - EastL + +description: + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC + is dedicated to memory-to-memory transfer through queue based + descriptor management. + +properties: + "#dma-cells": + minimum: 1 + # Should be enough + maximum: 255 + description: + Used to provide DMA controller specific information. + + compatible: + const: mediatek,cqdma + + reg: + minItems: 1 + maxItems: 255 + + interrupts: + minItems: 1 + maxItems: 255 + + clocks: + maxItems: 1 + + clock-names: + const: cqdma + + dma-channel-mask: + description: + Bitmask of available DMA channels in ascending order that are + not reserved by firmware and are available to the + kernel. i.e. first channel corresponds to LSB. + The first item in the array is for channels 0-31, the second is for + channels 32-63, etc. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 1 + # Should be enough + maxItems: 255 + + dma-channels: + $ref: /schemas/types.yaml#definitions/uint32 + description: + Number of DMA channels supported by the controller. + + dma-requests: + $ref: /schemas/types.yaml#definitions/uint32 + description: + Number of DMA request signals supported by the controller. + +required: + - "#dma-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dma-channel-mask + - dma-channels + - dma-requests + +additionalProperties: false + +examples: + - | + #include + #include + #include + cqdma: dma-controller@10212000 { + compatible = "mediatek,cqdma"; + reg = <0 0x10212000 0 0x80>, + <0 0x10212080 0 0x80>, + <0 0x10212100 0 0x80>; + interrupts = , + , + ; + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; + clock-names = "cqdma"; + dma-channel-mask = <63>; + dma-channels = <3>; + dma-requests = <32>; + #dma-cells = <1>; + }; + +...