From patchwork Tue Apr 21 00:11:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 201716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21C97C55185 for ; Tue, 21 Apr 2020 00:11:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 005622087E for ; Tue, 21 Apr 2020 00:11:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="E2KuNSBe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727019AbgDUAL3 (ORCPT ); Mon, 20 Apr 2020 20:11:29 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3540 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726954AbgDUAL1 (ORCPT ); Mon, 20 Apr 2020 20:11:27 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 20 Apr 2020 17:10:25 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 20 Apr 2020 17:11:27 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 20 Apr 2020 17:11:27 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 21 Apr 2020 00:11:26 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 21 Apr 2020 00:11:26 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 20 Apr 2020 17:11:26 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v8 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Date: Mon, 20 Apr 2020 17:11:13 -0700 Message-ID: <1587427874-3291-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587427874-3291-1-git-send-email-skomatineni@nvidia.com> References: <1587427874-3291-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587427825; bh=KEZ1lHNwQNYea9tamUq6xhOd3Wa4inGS2Z794lURij8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=E2KuNSBed2rb7qamv3KPQZgmPSMIcg4xeMxmE7ZfYvLa0mLXdw49YzLlBG6XH81yC 83T/ZWmIB+quM67kxe1dcSKofK3Io+tYLR/sq2tx9K4eHM/oli/GfW3Zhv8uso+TAF bRVH/uKbRk8ip1mXhpr8CyhYMyILXHxx2q9bdTUrx/5tFiILyucoy1lQvisvidju8E CzouZcvrrX3nZncidSVCUqcwjob9YUNvl9q59zbhLgnKhwuEakI618xiSHMWRHg0Up i5A/JwvaHwhw8dDCCbrvWa6PHxTfDEYLr/9FfmoIdOU3YCjXuWmdxi6tAp/th/cQ2w ehQE5P0dP0v6A== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds ID for Tegra210 VI controller reset to use with device tree. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/reset/tegra210-car.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 9dc84ec..8755946 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -10,5 +10,6 @@ #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) +#define TEGRA210_RST_VI 20 #endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */