From patchwork Fri Apr 17 05:23:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 201902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A128C2BB1D for ; Fri, 17 Apr 2020 05:23:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BDBB2063A for ; Fri, 17 Apr 2020 05:23:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Miljsmve" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726744AbgDQFXW (ORCPT ); Fri, 17 Apr 2020 01:23:22 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:39853 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726616AbgDQFXW (ORCPT ); Fri, 17 Apr 2020 01:23:22 -0400 X-UUID: 082516a55c7a46cdb85202acfad585f0-20200417 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=+zpT5B2IshhZ214mCSGdW/SvpDv7hKMz1rnXfEoTBUc=; b=MiljsmvesNAjTzcryn9BOY90EuXWSeTKVZOhLQHv7FCngg8UuCptbyLct3iyvUjQHsqjcgpWRhvQ7ZVVyvIiOt+Merq6p1BTp4CRTecvj1MfPUc1KF5Qbc/GxzTWtJV2dViDX0pLO7hRup40IQzF1hJUtVNaeymY3tKxv0bB9x8=; X-UUID: 082516a55c7a46cdb85202acfad585f0-20200417 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1199223011; Fri, 17 Apr 2020 13:23:17 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 17 Apr 2020 13:23:11 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 17 Apr 2020 13:23:12 +0800 From: Macpaul Lin To: Min Guo , Chunfeng Yun , Kishon Vijay Abraham I , Rob Herring , Matthias Brugger , , , , CC: Mediatek WSD Upstream , Macpaul Lin , Macpaul Lin Subject: [PATCH 2/2] phy: phy-mtk-tphy: introduce force_vbus for u2 phy Date: Fri, 17 Apr 2020 13:23:06 +0800 Message-ID: <1587100986-3104-2-git-send-email-macpaul.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1587100986-3104-1-git-send-email-macpaul.lin@mediatek.com> References: <1587100986-3104-1-git-send-email-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E815C42225B82684929207EFF6F91564BF86715E507A584A4955B6A5F960DCE12000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For some platforms, they don't have vbus pin connection between usb phy and mac. Hence we need to control force_vbus related registers to keep hardware works normal. This patch add corresponding behavior of force vbus in u2 phy related functions. Signed-off-by: Macpaul Lin --- drivers/phy/mediatek/phy-mtk-tphy.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.18.0 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index cdbcc49f7115..46f0fea175e5 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -99,6 +99,7 @@ #define U3P_U2PHYDTM1 0x06C #define P2C_RG_UART_EN BIT(16) +#define P2C_FORCE_VBUSVALID BIT(13) #define P2C_FORCE_IDDIG BIT(9) #define P2C_RG_VBUSVALID BIT(5) #define P2C_RG_SESSEND BIT(4) @@ -318,6 +319,7 @@ struct mtk_tphy { int nphys; int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ int src_coef; /* coefficient for slew rate calibrate */ + bool force_vbus; }; static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, @@ -611,13 +613,20 @@ static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, switch (mode) { case PHY_MODE_USB_DEVICE: tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; + if (tphy->force_vbus) + tmp |= P2C_RG_VBUSVALID | P2C_FORCE_VBUSVALID; break; case PHY_MODE_USB_HOST: tmp |= P2C_FORCE_IDDIG; - tmp &= ~P2C_RG_IDDIG; + if (tphy->force_vbus) + tmp &= ~(P2C_RG_VBUSVALID | P2C_FORCE_VBUSVALID); + else + tmp &= ~P2C_RG_IDDIG; break; case PHY_MODE_USB_OTG: tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); + if (tphy->force_vbus) + tmp &= ~(P2C_RG_VBUSVALID | P2C_FORCE_VBUSVALID); break; default: return; @@ -1187,6 +1196,11 @@ static int mtk_tphy_probe(struct platform_device *pdev) retval = PTR_ERR(instance->da_ref_clk); goto put_child; } + + /* + * On some platform, vbus is dis-connected between PHY and MAC. + */ + tphy->force_vbus = device_property_read_bool(dev, "force_vbus"); } provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);