From patchwork Thu Feb 20 16:24:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35C1DC11D11 for ; Thu, 20 Feb 2020 16:25:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0DC4B206F4 for ; Thu, 20 Feb 2020 16:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728589AbgBTQZl (ORCPT ); Thu, 20 Feb 2020 11:25:41 -0500 Received: from out28-194.mail.aliyun.com ([115.124.28.194]:52081 "EHLO out28-194.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728264AbgBTQZk (ORCPT ); Thu, 20 Feb 2020 11:25:40 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0850556|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.296506-0.0118045-0.69169; DS=CONTINUE|ham_system_inform|0.0103952-0.000395788-0.989209; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16370; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=23; RT=23; SR=0; TI=SMTPD_---.GqC0FCl_1582215911; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GqC0FCl_1582215911) by smtp.aliyun-inc.com(10.147.40.2); Fri, 21 Feb 2020 00:25:25 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, tglx@linutronix.de, ralf@linux-mips.org, paulburton@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, sboyd@kernel.org, mturquette@baylibre.com, mark.rutland@arm.com, robh+dt@kernel.org, daniel.lezcano@linaro.org, paul@crapouillou.net, geert+renesas@glider.be, krzk@kernel.org, ebiederm@xmission.com, miquel.raynal@bootlin.com, keescook@chromium.org, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, dongsheng.qiu@ingenic.com Subject: [PATCH v6 3/7] MIPS: CI20: Modify DTS to support high resolution timer for SMP. Date: Fri, 21 Feb 2020 00:24:45 +0800 Message-Id: <1582215889-113034-5-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for per core local timer, #2 for clocksource. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: No change. v2->v3: No change. v3->v4: Rebase on top of kernel 5.6-rc1. v4->v5: Move [5/6] in v4 to this patch, to ensure that we can git-bisect without ending up with a broken kernel. v5->v6: No change. arch/mips/boot/dts/ingenic/ci20.dts | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 37b9316..29437aa 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -455,7 +455,14 @@ }; &tcu { - /* 3 MHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; - assigned-clock-rates = <3000000>, <3000000>; + /* 3 MHz for the system timers, 750kHz for the clocksource */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>; + assigned-clock-rates = <3000000>, <3000000>, <750000>; + + /* + * Use channel #0 and #1 for the per core system timer, + * and use channel #2 for the clocksource. + */ + ingenic,pwm-channels-mask = <0xF8>; };