From patchwork Fri Jan 24 12:05:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 205392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D42AFC35242 for ; Fri, 24 Jan 2020 12:06:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B30AF206D4 for ; Fri, 24 Jan 2020 12:06:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388164AbgAXMGL (ORCPT ); Fri, 24 Jan 2020 07:06:11 -0500 Received: from out28-169.mail.aliyun.com ([115.124.28.169]:44913 "EHLO out28-169.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730215AbgAXMGK (ORCPT ); Fri, 24 Jan 2020 07:06:10 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1684902|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.688692-0.0149953-0.296313; DS=CONTINUE|ham_regular_dialog|0.00755407-0.000301436-0.992145; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16367; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=30; RT=30; SR=0; TI=SMTPD_---.Gh-0wLC_1579867533; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Gh-0wLC_1579867533) by smtp.aliyun-inc.com(10.147.40.2); Fri, 24 Jan 2020 20:06:03 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, tglx@linutronix.de, daniel.lezcano@linaro.org, shawnguo@kernel.org, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, miquel.raynal@bootlin.com, keescook@chromium.org, ebiederm@xmission.com, krzk@kernel.org, geert+renesas@glider.be, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, chenhc@lemote.com, jiaxun.yang@flygoat.com, paul@boddie.org.uk, hns@goldelico.com, mips-creator-ci20-dev@googlegroups.com, rick.tyliu@ingenic.com Subject: [PATCH v3 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding. Date: Fri, 24 Jan 2020 20:05:05 +0800 Message-Id: <1579867508-81499-5-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: Change the two Document from txt to yaml. v2->v3: Fix formatting errors. .../bindings/mips/ingenic/ingenic,cpu.yaml | 53 ++++++++++++++++++++++ .../bindings/mips/ingenic/ingenic,soc,yaml | 35 ++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml new file mode 100644 index 00000000..014c2b5 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic XBurst family CPUs + +maintainers: + - 周琰杰 (Zhou Yanjie) +description: | + Ingenic XBurst family CPUs shall have the following properties. + +properties: + compatible: + oneOf: + - ingenic,xburst + - ingenic,xburst2 + + reg: + description: | + The number of the CPU. + +required: + - device_type + - compatible + - reg + +Example: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu JZ4780_CLK_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <1>; + + clocks = <&cgu JZ4780_CLK_CORE1>; + clock-names = "cpu"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml new file mode 100644 index 00000000..324c4bb --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic SoCs with XBurst CPU inside. + +maintainers: + - 周琰杰 (Zhou Yanjie) +description: | + Ingenic SoCs with XBurst CPU inside shall have the following properties. + +properties: + compatible: + oneOf: + - ingenic,jz4740 + - ingenic,jz4725b + - ingenic,jz4760 + - ingenic,jz4760b + - ingenic,jz4770 + - ingenic,jz4780 + - ingenic,x1000 + - ingenic,x1000e + - ingenic,x1500 + +required: + - compatible + +examples: + - | + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4780"; +...