From patchwork Thu Jan 2 04:00:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 206262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56DD5C3276D for ; Thu, 2 Jan 2020 04:03:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E9E720863 for ; Thu, 2 Jan 2020 04:03:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jp7M8Fml" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727652AbgABECX (ORCPT ); Wed, 1 Jan 2020 23:02:23 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:21283 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727617AbgABECX (ORCPT ); Wed, 1 Jan 2020 23:02:23 -0500 X-UUID: 39791f4b2e614a41b3bdd965e4ca986c-20200102 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WZibcIXENQqD/QYNVuPSeY7uijgfthNFPSvOXqGUZGw=; b=jp7M8FmlNmDz3OW65YDTq0AfPd/VHZP3aSVtHmK9A5iEEhpPUji99/TDydcv+R5uSIP5yqa3MfSc9WPsnkescX/IXcEwyE9BhFjOON22XrGO77PJ5Y+goyBq+Wgws8MHI/vgz5i/Zq2gFAlywrj5iGEqF/mUDR1YK8Q+od1Ltms=; X-UUID: 39791f4b2e614a41b3bdd965e4ca986c-20200102 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1902967522; Thu, 02 Jan 2020 12:02:17 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 2 Jan 2020 12:01:50 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 2 Jan 2020 12:01:35 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [PATCH v6, 03/14] drm/mediatek: make sout select function format same with select input Date: Thu, 2 Jan 2020 12:00:13 +0800 Message-ID: <1577937624-14313-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1577937624-14313-1-git-send-email-yongqiang.niu@mediatek.com> References: <1577937624-14313-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org there will be more sout case in the future, make the sout function format same mtk_ddp_sel_in Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) -- 1.8.1.1.dirty diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 91c9b19..f99f89a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -389,17 +389,23 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, return value; } -static void mtk_ddp_sout_sel(struct regmap *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) +static unsigned int mtk_ddp_sout_sel(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) { + unsigned int value; + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL, - BLS_TO_DSI_RDMA1_TO_DPI1); + *addr = DISP_REG_CONFIG_OUT_SEL; + value = BLS_TO_DSI_RDMA1_TO_DPI1; } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL, - BLS_TO_DPI_RDMA1_TO_DSI); + *addr = DISP_REG_CONFIG_OUT_SEL; + value = BLS_TO_DPI_RDMA1_TO_DSI; + } else { + value = 0; } + + return value; } void mtk_ddp_add_comp_to_path(struct regmap *config_regs, @@ -412,7 +418,9 @@ void mtk_ddp_add_comp_to_path(struct regmap *config_regs, if (value) regmap_update_bits(config_regs, addr, value, value); - mtk_ddp_sout_sel(config_regs, cur, next); + value = mtk_ddp_sout_sel(cur, next, &addr); + if (value) + regmap_update_bits(config_regs, addr, value, value); value = mtk_ddp_sel_in(cur, next, &addr); if (value)